diff options
| author | Paul Burton | 2015-01-29 01:28:03 +0000 |
|---|---|---|
| committer | Daniel Schwierzeck | 2015-01-29 12:55:01 +0100 |
| commit | 8755d50706742e4d302a335f4e69dd6430ec12a2 (patch) | |
| tree | b7730ef7f29fc91b729413d7f447075972f3a2f3 /arch/mips/lib/cache_init.S | |
| parent | dd7c72006e51f0d27e5cb1dcf60d5b9bf307565e (diff) | |
MIPS: clear TagLo select 2 during cache init
Current MIPS cores from Imagination Technologies use TagLo select 2 for
the data cache. The architecture requires that it is safe for software
to write to this register even if it isn't present, so take the trivial
option of clearing both selects 0 & 2.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch/mips/lib/cache_init.S')
| -rw-r--r-- | arch/mips/lib/cache_init.S | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 04a36b25288..137d7283ffe 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -139,6 +139,14 @@ LEAF(mips_cache_reset) #endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */ /* + * The TagLo registers used depend upon the CPU implementation, but the + * architecture requires that it is safe for software to write to both + * TagLo selects 0 & 2 covering supported cases. + */ + mtc0 zero, CP0_TAGLO + mtc0 zero, CP0_TAGLO, 2 + + /* * The caches are probably in an indeterminate state, so we force good * parity into them by doing an invalidate for each line. If * CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is set then we'll proceed to @@ -151,7 +159,6 @@ LEAF(mips_cache_reset) * Initialize the I-cache first, */ blez t2, 1f - mtc0 zero, CP0_TAGLO PTR_LI t0, INDEX_BASE PTR_ADDU t1, t0, t2 /* clear tag to invalidate */ @@ -169,7 +176,6 @@ LEAF(mips_cache_reset) * then initialize D-cache. */ 1: blez t3, 3f - mtc0 zero, CP0_TAGLO PTR_LI t0, INDEX_BASE PTR_ADDU t1, t0, t3 /* clear all tags */ |