diff options
| author | Lars Povlsen | 2020-02-06 10:45:40 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck | 2020-04-09 18:55:59 +0200 |
| commit | 7048bb13b2d6309ef8386fca665247d3afa36ab0 (patch) | |
| tree | 236eb7433c2c06d3469b0bce455f1e569ef3095f /arch/mips/mach-mscc/include | |
| parent | ea148789318c8152acb0a3974d4a8342dbd6b901 (diff) | |
mips: vcoreiii: Fix cache coherency issues
This patch fixes an stability issue seen on some vcoreiii targets,
which was root caused to a cache inconsistency situation.
The inconsistency was caused by having kuseg pointing to NOR area but
used as a stack/gd/heap area during initialization, while only
relatively late remapping the RAM area into kuseg position.
The fix is to initialize the DDR right after the TLB setup, and then
remapping it into position before gd/stack/heap usage.
Reported-by: Ramin Seyed-Moussavi <ramin.moussavi@yacoub.de>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Diffstat (limited to 'arch/mips/mach-mscc/include')
| -rw-r--r-- | arch/mips/mach-mscc/include/mach/ddr.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index d1f4287f654..bf75e52ec3c 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -435,16 +435,12 @@ static inline void hal_vcoreiii_ddr_failed(void) reset = KSEG0ADDR(_machine_restart); icache_lock((void *)reset, 128); asm volatile ("jr %0"::"r" (reset)); - - panic("DDR init failed\n"); } #else /* JR2 || ServalT */ static inline void hal_vcoreiii_ddr_failed(void) { writel(0, BASE_CFG + ICPU_RESET); writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST); - - panic("DDR init failed\n"); } #endif |