mips: mt76xx: Remove cache workaround and select SYS_MALLOC_CLEAR_ON_INIT

With commit 06985289d452 ("watchdog: Implement generic watchdog_reset()
version") the init sequence has changed in arch_misc_init(), resulting
in a re-appearance of the d-cache issue on MT7688 boards (e.g. gardena).
When this happens, the first (or sometimes later ones as well) TFTP
command hangs and does not complete correctly. This leads to the
assumption that the d-cache is not in a clean state once the ethernet
driver is called (d-cache is used here for the buffers). The old work-
around with the cache flush somehow does not work any more now with
the new code change.

To fix this issue, this patch now removes the old workaround and selects
CONFIG_SYS_MALLOC_CLEAR_ON_INIT for ARCH_MTMIPS. With this option the
complete malloc area is initialized with zeros (cache lines are touched).
Testing has shown that this also fixes the issue on the MT7688 boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Suggested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

1 files changed, 0 insertions, 15 deletions

diff --git a/arch/mips/mach-mtmips/cpu.c b/arch/mips/mach-mtmips/cpu.c
index fcd0484a6d8..b0a6397d68f 100644
--- a/arch/mips/mach-mtmips/cpu.c
+++ b/arch/mips/mach-mtmips/cpu.c
@@ -68,18 +68,3 @@ int print_cpuinfo(void)
 
 	return 0;
 }
-
-int arch_misc_init(void)
-{
-	/*
-	 * It has been noticed, that sometimes the d-cache is not in a
-	 * "clean-state" when U-Boot is running on MT7688. This was
-	 * detected when using the ethernet driver (which uses d-cache)
-	 * and a TFTP command does not complete. Flushing the complete
-	 * d-cache (again?) here seems to fix this issue.
-	 */
-	flush_dcache_range(gd->bd->bi_memstart,
-			   gd->bd->bi_memstart + gd->ram_size - 1);
-
-	return 0;
-}