diff options
| author | Ruchika Gupta | 2017-03-02 14:12:41 +0530 |
|---|---|---|
| committer | York Sun | 2017-04-17 09:03:30 -0700 |
| commit | 668ec87f523580c981a01b06560f70cd5a52e2c9 (patch) | |
| tree | 170b1bf6ea3a8078a90b060e205804abd50d6792 /arch/powerpc/cpu/mpc85xx/start.S | |
| parent | 3d91f46ca84f6b4a667a41ac1957aebf60764002 (diff) | |
powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram
For E6500 cores, L2 cache has been used as init_ram. L1 cache is a
write through cache on E6500.If lines are not locked in both L1 and
L2 caches, crashes are observed during secure boot. This patch locks/
unlocks both L1 and L2 cache to prevent the crash.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/start.S')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index eb817f1e86f..63fdffddb1a 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1145,8 +1145,9 @@ switch_as: li r0,0 1: dcbz r0,r3 -#ifdef CONFIG_E6500 /* Lock/unlock L2 cache instead of L1 */ +#ifdef CONFIG_E6500 /* Lock/unlock L2 cache long with L1 */ dcbtls 2, r0, r3 + dcbtls 0, r0, r3 #else dcbtls 0, r0, r3 #endif @@ -1790,8 +1791,9 @@ unlock_ram_in_cache: slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) mtctr r4 1: dcbi r0,r3 -#ifdef CONFIG_E6500 /* lock/unlock L2 cache instead of L1 */ +#ifdef CONFIG_E6500 /* lock/unlock L2 cache long with L1 */ dcblc 2, r0, r3 + dcblc 0, r0, r3 #else dcblc r0,r3 #endif |