diff options
| author | Stefan Roese | 2011-11-15 08:02:37 +0000 |
|---|---|---|
| committer | Wolfgang Denk | 2011-11-16 21:15:59 +0100 |
| commit | 4a1272662adf5970ebd78ab7590d970f621e05ec (patch) | |
| tree | 638a1de923303fa2c64f80d0a60a380f5cdb61ac /arch/powerpc/cpu/ppc4xx | |
| parent | deeecb7c7edc2ea7e7dda6742ed221cdd6fa3ba2 (diff) | |
40x_spd_sdram.c: Fix GCC 4.6 build warnings
Fix:
40x_spd_sdram.c: In function 'spd_sdram':
40x_spd_sdram.c:137:6: warning: variable 'sdram0_b3cr' set but not used [-Wunused-but-set-variable]
40x_spd_sdram.c:136:6: warning: variable 'sdram0_b2cr' set but not used [-Wunused-but-set-variable]
40x_spd_sdram.c:129:6: warning: variable 'sdram0_ecccfg' set but not used [-Wunused-but-set-variable]
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/powerpc/cpu/ppc4xx')
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c index a31b17e9e89..48aa75391df 100644 --- a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c +++ b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c @@ -116,26 +116,25 @@ long int spd_sdram(int(read_spd)(uint addr)) { int tmp,row,col; int total_size,bank_size,bank_code; - int ecc_on; int mode; int bank_cnt; int sdram0_pmit=0x07c00000; + int sdram0_b0cr; + int sdram0_b1cr = 0; #ifndef CONFIG_405EP /* not on PPC405EP */ + int sdram0_b2cr = 0; + int sdram0_b3cr = 0; int sdram0_besr0 = -1; int sdram0_besr1 = -1; int sdram0_eccesr = -1; -#endif int sdram0_ecccfg; + int ecc_on; +#endif int sdram0_rtr=0; int sdram0_tr=0; - int sdram0_b0cr; - int sdram0_b1cr; - int sdram0_b2cr; - int sdram0_b3cr; - int sdram0_cfg=0; int t_rp; @@ -295,6 +294,7 @@ long int spd_sdram(int(read_spd)(uint addr)) if (bank_cnt > 4) /* we only have 4 banks to work with */ SPD_ERR("SDRAM - unsupported module rows for this width\n"); +#ifndef CONFIG_405EP /* not on PPC405EP */ /* now check for ECC ability of module. We only support ECC * on 32 bit wide devices with 8 bit ECC. */ @@ -305,6 +305,7 @@ long int spd_sdram(int(read_spd)(uint addr)) sdram0_ecccfg = 0; ecc_on = 0; } +#endif /*------------------------------------------------------------------ * calculate total size @@ -378,9 +379,6 @@ long int spd_sdram(int(read_spd)(uint addr)) * using the calculated values, compute the bank * config register values. * -------------------------------------------------------------------*/ - sdram0_b1cr = 0; - sdram0_b2cr = 0; - sdram0_b3cr = 0; /* compute the size of each bank */ bank_size = total_size / bank_cnt; @@ -444,8 +442,10 @@ long int spd_sdram(int(read_spd)(uint addr)) /* SDRAM have a power on delay, 500 micro should do */ udelay(500); sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR; +#ifndef CONFIG_405EP /* not on PPC405EP */ if (ecc_on) sdram0_cfg |= SDRAM0_CFG_MEMCHK; +#endif mtsdram(SDRAM0_CFG, sdram0_cfg); return (total_size); |