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authorChristophe Leroy2024-04-12 12:01:25 +0200
committerChristophe Leroy2024-04-18 15:47:46 +0200
commitc58074af2ef93dbf4d6e6164d51eefbf562fe7c5 (patch)
tree29b1f8a3ea1a7d8dac99c64f5dff9c54e31e326f /arch/powerpc/dts
parentc578728d2e33754e38af869f6cdf992d18d058da (diff)
board: cssi: Add support for SPI bus on MCR3000 board
MCR3000 board has some components tied to the SPI bus, like the Texas Instruments LM74 temperature sensor. Add support for SPI bus. The SPI chipselects are a bit special in the way that they are driven by 3 bits in a register of the board's CPLD where the value writen in those bits exclusively activates one of the 7 possible chipselects and value 0 sets all chipselets to inactive. So add a special GPIO driver that simulates GPIOs for those chipselect. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Diffstat (limited to 'arch/powerpc/dts')
-rw-r--r--arch/powerpc/dts/mcr3000.dts31
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/powerpc/dts/mcr3000.dts b/arch/powerpc/dts/mcr3000.dts
index c4d7737bc67..edcd8358d09 100644
--- a/arch/powerpc/dts/mcr3000.dts
+++ b/arch/powerpc/dts/mcr3000.dts
@@ -26,6 +26,37 @@
timeout-sec = <2>;
hw_margin_ms = <1000>;
};
+
+ spi: spi@aa0 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl,mpc8xx-spi";
+ };
+ };
+
+ localbus@ff000100 {
+ compatible = "s3k,mcr3000-localbus", "fsl,pq1-localbus", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <0xff000100 0x40>; // ORx and BRx register
+
+ ranges = <0 0 0x04000000 0x04000000 // BOOT
+ 1 0 0x00000000 0x04000000 // SDRAM
+ 2 0 0x08000000 0x04000000 // RAMDP
+ 3 0 0x0C000000 0x04000000 // NAND
+ 4 0 0x10000000 0x04000000 // Periphs
+ 5 0 0x14000000 0x04000000 // FPGA
+ 6 0 0x18000000 0x04000000 // mezzanine
+ 7 0 0x1c000000 0x04000000>; // DSP
+
+ csspi: gpio-controller@2 {
+ #gpio-cells = <2>;
+ compatible = "s3k,mcr3000-cpld-csspi";
+ reg = <4 0x802 2>;
+ gpio-controller;
+ };
};
SERIAL: smc@0 {