diff options
author | Stefan Roese | 2012-09-19 14:33:52 +0200 |
---|---|---|
committer | Tom Rini | 2012-10-15 11:53:59 -0700 |
commit | 99bcad1809d073a7ec5a6f8ed49637693904e2de (patch) | |
tree | 9516e894a30ca0cff3f7b88bfe3e5d2e9e3d42ab /arch/powerpc/include | |
parent | f2760c4acd5b7a198632d002528ec7c227ea27b8 (diff) |
ppc4xx: Remove IOP480 support
Since the IOP480 (PPC401/3 variant from PLX) is only used on 2
boards that are not actively maintained, lets remove support
for it completely. This way the ppc4xx code will get a bit cleaner.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r-- | arch/powerpc/include/asm/cache.h | 2 | ||||
-rw-r--r-- | arch/powerpc/include/asm/ppc405.h | 4 |
2 files changed, 1 insertions, 5 deletions
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index e6b8f69b765..5f9c640aa2a 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -8,7 +8,7 @@ #include <asm/processor.h> /* bytes per L1 cache line */ -#if defined(CONFIG_8xx) || defined(CONFIG_IOP480) +#if defined(CONFIG_8xx) #define L1_CACHE_SHIFT 4 #elif defined(CONFIG_PPC64BRIDGE) #define L1_CACHE_SHIFT 7 diff --git a/arch/powerpc/include/asm/ppc405.h b/arch/powerpc/include/asm/ppc405.h index 14a7a379fd1..892848aacf1 100644 --- a/arch/powerpc/include/asm/ppc405.h +++ b/arch/powerpc/include/asm/ppc405.h @@ -28,11 +28,7 @@ #define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) #define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) -#ifndef CONFIG_IOP480 #define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ -#else -#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480(403)*/ -#endif /* DCR registers */ #define PLB0_ACR 0x0087 |