ppc: Remove T2081QDS board and ARCH_T2081 support

This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.  It is also the only ARCH_T2081 board so remove that support
as well.

Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

6 files changed, 6 insertions, 49 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 124c22f58a5..f7679f7ea1b 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -210,14 +210,6 @@ config TARGET_T2080RDB
 	imply CMD_SATA
 	imply PANIC_HANG
 
-config TARGET_T2081QDS
-	bool "Support T2081QDS"
-	select ARCH_T2081
-	select SUPPORT_SPL
-	select PHYS_64BIT
-	select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
-	select FSL_DDR_INTERACTIVE
-
 config TARGET_T4160RDB
 	bool "Support T4160RDB"
 	select ARCH_T4160
@@ -928,29 +920,6 @@ config ARCH_T2080
 	imply CMD_REGINFO
 	imply FSL_SATA
 
-config ARCH_T2081
-	bool
-	select E500MC
-	select E6500
-	select FSL_LAW
-	select SYS_FSL_DDR_VER_47
-	select SYS_FSL_ERRATUM_A006379
-	select SYS_FSL_ERRATUM_A006593
-	select SYS_FSL_ERRATUM_A007186
-	select SYS_FSL_ERRATUM_A007212
-	select SYS_FSL_ERRATUM_A009942
-	select SYS_FSL_ERRATUM_ESDHC111
-	select FSL_PCIE_RESET
-	select SYS_FSL_HAS_DDR3
-	select SYS_FSL_HAS_SEC
-	select SYS_FSL_QORIQ_CHASSIS2
-	select SYS_FSL_SEC_BE
-	select SYS_FSL_SEC_COMPAT_4
-	select SYS_PPC64
-	select FSL_IFC
-	imply CMD_NAND
-	imply CMD_REGINFO
-
 config ARCH_T4160
 	bool
 	select E500MC
@@ -1052,8 +1021,7 @@ config MAX_CPUS
 		     ARCH_P5040 || \
 		     ARCH_T1040 || \
 		     ARCH_T1042 || \
-		     ARCH_T2080 || \
-		     ARCH_T2081
+		     ARCH_T2080
 	default 2 if ARCH_B4420 || \
 		     ARCH_BSC9132 || \
 		     ARCH_MPC8572 || \
@@ -1110,7 +1078,6 @@ config SYS_CCSRBAR_DEFAULT
 				ARCH_T1040	|| \
 				ARCH_T1042	|| \
 				ARCH_T2080	|| \
-				ARCH_T2081	|| \
 				ARCH_T4160	|| \
 				ARCH_T4240
 	default 0xe0000000 if ARCH_QEMU_E500
@@ -1297,7 +1264,6 @@ config SYS_FSL_NUM_LAWS
 			ARCH_P5020	|| \
 			ARCH_P5040	|| \
 			ARCH_T2080	|| \
-			ARCH_T2081	|| \
 			ARCH_T4160	|| \
 			ARCH_T4240
 	default 16 if	ARCH_T1023	|| \
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 14e46626f33..30dd1b4c2cb 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -51,7 +51,6 @@ obj-$(CONFIG_ARCH_T1042)	+= t1040_ids.o
 obj-$(CONFIG_ARCH_T1023) += t1024_ids.o
 obj-$(CONFIG_ARCH_T1024) += t1024_ids.o
 obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
-obj-$(CONFIG_ARCH_T2081) += t2080_ids.o
 
 
 obj-$(CONFIG_QE)	+= qe_io.o
@@ -90,7 +89,6 @@ obj-$(CONFIG_ARCH_T1042)	+= t1040_serdes.o
 obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o
 obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
 obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o
-obj-$(CONFIG_ARCH_T2081) += t2080_serdes.o
 
 obj-y	+= cpu.o
 obj-y	+= cpu_init.o
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 9c89ce5d70e..59a007b4913 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -127,7 +127,7 @@ void get_sys_info(sys_info_t *sys_info)
 	 * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
 	 */
 #if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
-	defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
+	defined(CONFIG_ARCH_T2080)
 	svr = get_svr();
 	switch (SVR_SOC_VER(svr)) {
 	case SVR_T4240:
@@ -198,7 +198,7 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 
 #if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
-	defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
+	defined(CONFIG_ARCH_T2080)
 #define FM1_CLK_SEL	0xe0000000
 #define FM1_CLK_SHIFT	29
 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
index 32cfcc0242b..5f34aab4531 100644
--- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
@@ -160,7 +160,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 	{}
 };
 
-#ifndef CONFIG_ARCH_T2081
 static const struct serdes_config serdes2_cfg_tbl[] = {
 	/* SerDes 2 */
 	{0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
@@ -176,13 +175,10 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 	{0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
 	{}
 };
-#endif
 
 static const struct serdes_config *serdes_cfg_tbl[] = {
 	serdes1_cfg_tbl,
-#ifndef CONFIG_ARCH_T2081
 	serdes2_cfg_tbl,
-#endif
 };
 
 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 4d70259f09b..f7ab5e3f65e 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -364,7 +364,7 @@
 #define QE_NUM_OF_SNUM			28
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
-#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
+#elif defined(CONFIG_ARCH_T2080)
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
@@ -381,9 +381,6 @@
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
-#elif defined(CONFIG_ARCH_T2081)
-#define CONFIG_SYS_NUM_FM1_DTSEC	6
-#define CONFIG_SYS_NUM_FM1_10GEC	2
 #endif
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 #define CONFIG_PME_PLAT_CLK_DIV		1
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 905613fa312..3fc56ef0c14 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1808,7 +1808,7 @@ typedef struct ccsr_gur {
 #define PXCKEN_MASK				0x80000000
 #define PXCK_MASK				0x00FF0000
 #define PXCK_BITS_START				16
-#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
+#elif defined(CONFIG_ARCH_T2080)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xff000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	24
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL		0x00ff0000
@@ -1880,7 +1880,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII	0x08000000
 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO		0x10000000
 #endif
-#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
+#if defined(CONFIG_ARCH_T2080)
 #define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418 */
 #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII	0x00000000
 #define FSL_CORENET_RCWSR13_EC1_GPIO		0x40000000