diff options
| author | Tom Rini | 2016-05-25 07:19:31 -0400 |
|---|---|---|
| committer | Tom Rini | 2016-05-25 07:19:31 -0400 |
| commit | 826d06dbdd0e29ab0d8bd76d1ca640e2dfdb076c (patch) | |
| tree | 01a7f2b3f69119bb26e72040ae52f91e32d68adc /arch/powerpc | |
| parent | fc15b9beed05dec6cc092c265042381a0eadb0e9 (diff) | |
| parent | 8ef548d5f13e68e1b3975d9b68920bfa8bf09891 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 23 | ||||
| -rw-r--r-- | arch/powerpc/lib/ppccache.S | 4 |
2 files changed, 27 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 82a151a0d0e..4c512258685 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -720,16 +720,39 @@ enable_l2_cluster_l2: ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l sync stw r4, 0(r3) /* invalidate L2 */ + /* Poll till the bits are cleared */ 1: sync lwz r0, 0(r3) twi 0, r0, 0 isync and. r1, r0, r4 bne 1b + + /* L2PE must be set before L2 cache is enabled */ + lis r4, (L2CSR0_L2PE)@h + ori r4, r4, (L2CSR0_L2PE)@l + sync + stw r4, 0(r3) /* enable L2 parity/ECC error checking */ + /* Poll till the bit is set */ +1: sync + lwz r0, 0(r3) + twi 0, r0, 0 + isync + and. r1, r0, r4 + beq 1b + lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h ori r4, r4, (L2CSR0_L2REP_MODE)@l sync stw r4, 0(r3) /* enable L2 */ + /* Poll till the bit is set */ +1: sync + lwz r0, 0(r3) + twi 0, r0, 0 + isync + and. r1, r0, r4 + beq 1b + delete_ccsr_l2_tlb: delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 #endif diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S index b96dbc60e09..66cf02dbd04 100644 --- a/arch/powerpc/lib/ppccache.S +++ b/arch/powerpc/lib/ppccache.S @@ -65,6 +65,7 @@ ppcSync: * flush_dcache_range(unsigned long start, unsigned long stop) */ _GLOBAL(flush_dcache_range) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx) li r5,L1_CACHE_BYTES-1 andc r3,r3,r5 subf r4,r3,r4 @@ -77,6 +78,7 @@ _GLOBAL(flush_dcache_range) addi r3,r3,L1_CACHE_BYTES bdnz 1b sync /* wait for dcbst's to get to ram */ +#endif blr /* @@ -87,6 +89,7 @@ _GLOBAL(flush_dcache_range) * invalidate_dcache_range(unsigned long start, unsigned long stop) */ _GLOBAL(invalidate_dcache_range) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx) li r5,L1_CACHE_BYTES-1 andc r3,r3,r5 subf r4,r3,r4 @@ -100,5 +103,6 @@ _GLOBAL(invalidate_dcache_range) addi r3,r3,L1_CACHE_BYTES bdnz 1b sync /* wait for dcbi's to get to ram */ +#endif blr |