ppc: Remove MPC8555CDS boards

These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM.  Remove them.  As this is the only
ARCH_MPC8555 platform left, remove that support as well.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

7 files changed, 5 insertions, 52 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 0b138569528..891db4e3781 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -49,11 +49,6 @@ config TARGET_MPC8548CDS
 	select ARCH_MPC8548
 	select FSL_VIA
 
-config TARGET_MPC8555CDS
-	bool "Support MPC8555CDS"
-	select ARCH_MPC8555
-	select FSL_VIA
-
 config TARGET_MPC8568MDS
 	bool "Support MPC8568MDS"
 	select ARCH_MPC8568
@@ -388,14 +383,6 @@ config ARCH_MPC8548
 	select SYS_PPC_E500_USE_DEBUG_TLB
 	imply CMD_REGINFO
 
-config ARCH_MPC8555
-	bool
-	select FSL_LAW
-	select SYS_FSL_HAS_DDR1
-	select SYS_FSL_HAS_SEC
-	select SYS_FSL_SEC_BE
-	select SYS_FSL_SEC_COMPAT_2
-
 config ARCH_MPC8560
 	bool
 	select FSL_LAW
@@ -948,7 +935,6 @@ config SYS_CCSRBAR_DEFAULT
 				ARCH_MPC8540	|| \
 				ARCH_MPC8544	|| \
 				ARCH_MPC8548	|| \
-				ARCH_MPC8555	|| \
 				ARCH_MPC8560	|| \
 				ARCH_MPC8568	|| \
 				ARCH_MPC8572	|| \
@@ -1179,7 +1165,6 @@ config SYS_FSL_NUM_LAWS
 			ARCH_MPC8548	|| \
 			ARCH_MPC8568
 	default 8 if	ARCH_MPC8540	|| \
-			ARCH_MPC8555	|| \
 			ARCH_MPC8560
 	help
 		Number of local access windows. This is fixed per SoC.
@@ -1253,7 +1238,7 @@ config SYS_FSL_LBC_CLK_DIV
 	int "Divider of platform clock"
 	depends on FSL_ELBC || ARCH_MPC8540 || \
 		ARCH_MPC8548 || \
-		ARCH_MPC8555 || ARCH_MPC8560 || \
+		ARCH_MPC8560 || \
 		ARCH_MPC8568
 
 	default 2 if	ARCH_P2041	|| \
@@ -1272,7 +1257,6 @@ config FSL_VIA
 source "board/emulation/qemu-ppce500/Kconfig"
 source "board/freescale/corenet_ds/Kconfig"
 source "board/freescale/mpc8548cds/Kconfig"
-source "board/freescale/mpc8555cds/Kconfig"
 source "board/freescale/mpc8568mds/Kconfig"
 source "board/freescale/p1010rdb/Kconfig"
 source "board/freescale/p1_p2_rdb_pc/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index e8126c98f89..610a8ec43f5 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -301,8 +301,7 @@ int checkcpu (void)
 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 /* Everything after the first generation of PQ3 parts has RSTCR */
-#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8555) || \
-	defined(CONFIG_ARCH_MPC8560)
+#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
 	unsigned long val, msr;
 
 	/*
diff --git a/arch/powerpc/cpu/mpc85xx/pci.c b/arch/powerpc/cpu/mpc85xx/pci.c
index 559730181ef..b7835c0fee5 100644
--- a/arch/powerpc/cpu/mpc85xx/pci.c
+++ b/arch/powerpc/cpu/mpc85xx/pci.c
@@ -120,29 +120,6 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
 
 	pci_register_hose(hose);
 
-#if defined(CONFIG_TARGET_MPC8555CDS)
-	/*
-	 * This is a SW workaround for an apparent HW problem
-	 * in the PCI controller on the MPC85555/41 CDS boards.
-	 * The first config cycle must be to a valid, known
-	 * device on the PCI bus in order to trick the PCI
-	 * controller state machine into a known valid state.
-	 * Without this, the first config cycle has the chance
-	 * of hanging the controller permanently, just leaving
-	 * it in a semi-working state, or leaving it working.
-	 *
-	 * Pick on the Tundra, Device 17, to get it right.
-	 */
-	{
-		u8 header_type;
-
-		pci_hose_read_config_byte(hose,
-					  PCI_BDF(0,BRIDGE_ID,0),
-					  PCI_HEADER_TYPE,
-					  &header_type);
-	}
-#endif
-
 	hose->last_busno = pci_hose_scan(hose);
 
 #ifdef CONFIG_MPC85XX_PCI2
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 90c9fe1af51..26067dd7132 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -607,8 +607,7 @@ int get_clocks(void)
 	 * for that SOC. This information is taken from application note
 	 * AN2919.
 	 */
-#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560) || \
-	defined(CONFIG_ARCH_MPC8555)
+#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
 	gd->arch.i2c1_clk = sys_info.freq_systembus;
 #elif defined(CONFIG_ARCH_MPC8544)
 	/*
diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h
index e6f1fab5fb9..d42469c6e05 100644
--- a/arch/powerpc/include/asm/cpm_85xx.h
+++ b/arch/powerpc/include/asm/cpm_85xx.h
@@ -77,13 +77,8 @@
  */
 #define CPM_DATAONLY_BASE	((uint)128)
 #define CPM_DP_NOSPACE		((uint)0x7FFFFFFF)
-#if defined(CONFIG_ARCH_MPC8555)
-#define CPM_FCC_SPECIAL_BASE	((uint)0x00009000)
-#define CPM_DATAONLY_SIZE	((uint)(8 * 1024) - CPM_DATAONLY_BASE)
-#else	/* MPC8540, MPC8560 */
 #define CPM_FCC_SPECIAL_BASE	((uint)0x0000B000)
 #define CPM_DATAONLY_SIZE	((uint)(16 * 1024) - CPM_DATAONLY_BASE)
-#endif
 
 /* The number of pages of host memory we allocate for CPM.  This is
  * done early in kernel initialization to get physically contiguous
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index ae176082760..3b26451928a 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -325,7 +325,7 @@ void lbc_sdram_init(void);
 #define LCRR_CLKDIV			0x0000001F
 #define LCRR_CLKDIV_SHIFT		0
 #if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
-	defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
+	defined(CONFIG_ARCH_MPC8560)
 #define LCRR_CLKDIV_2			0x00000002
 #define LCRR_CLKDIV_4			0x00000004
 #define LCRR_CLKDIV_8			0x00000008
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index b6770c4cf4d..1411b3f38b9 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -124,8 +124,7 @@ typedef struct ccsr_i2c {
 } ccsr_i2c_t;
 
 #if defined(CONFIG_ARCH_MPC8540) || \
-	defined(CONFIG_ARCH_MPC8548) || \
-	defined(CONFIG_ARCH_MPC8555)
+	defined(CONFIG_ARCH_MPC8548)
 /* DUART Registers */
 typedef struct ccsr_duart {
 	u8	res1[1280];