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authorBin Meng2018-09-26 06:55:13 -0700
committerAndes2018-10-03 17:47:43 +0800
commitce7a8e0740f1f9ec915109392184d335ba231448 (patch)
treede9a9a5c0811e6e59f40a39faf3db60cb143250d /arch/riscv/config.mk
parent3d6015651bcb09d2a26e325e533c78525140d613 (diff)
riscv: Explicitly pass -march and -mabi to the compiler
At present the compiler flag against which architecture and abi variant the riscv image is built for is not explicitly indicated which means the default compiler configuration is used. But this does not work if we want to build a different target (eg: 32-bit riscv images using a toolchain configured for 64-bit riscv). Fix this by explicitly passing -march and -mabi to the compiler. Since generically we don't use floating point in U-Boot, specify the RV[32|64]IMA ISA and software floating ABI. This also fix some alignment coding style issues. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Diffstat (limited to 'arch/riscv/config.mk')
-rw-r--r--arch/riscv/config.mk8
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk
index c0b3858edd9..b235ae1413d 100644
--- a/arch/riscv/config.mk
+++ b/arch/riscv/config.mk
@@ -18,12 +18,16 @@ endif
64bit-emul := elf64lriscv
ifdef CONFIG_32BIT
+PLATFORM_CPPFLAGS += -march=rv32ima -mabi=ilp32
PLATFORM_LDFLAGS += -m $(32bit-emul)
+CFLAGS_EFI += -march=rv32ima -mabi=ilp32
EFI_LDS := elf_riscv32_efi.lds
endif
ifdef CONFIG_64BIT
+PLATFORM_CPPFLAGS += -march=rv64ima -mabi=lp64
PLATFORM_LDFLAGS += -m $(64bit-emul)
+CFLAGS_EFI += -march=rv64ima -mabi=lp64
EFI_LDS := elf_riscv64_efi.lds
endif
@@ -31,8 +35,8 @@ CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \
-T $(srctree)/examples/standalone/riscv.lds
PLATFORM_CPPFLAGS += -ffixed-gp -fpic
-PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections
-LDFLAGS_u-boot += --gc-sections -static -pie
+PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections
+LDFLAGS_u-boot += --gc-sections -static -pie
EFI_CRT0 := crt0_riscv_efi.o
EFI_RELOC := reloc_riscv_efi.o