diff options
| author | Sean Anderson | 2020-06-24 06:41:19 -0400 |
|---|---|---|
| committer | Andes | 2020-07-01 15:01:22 +0800 |
| commit | b8bc120927a75ccbdd3a242555933dc644391bc8 (patch) | |
| tree | c45afd3e5baf6fe2c64ce1a35125eee0b240d313 /arch/riscv/cpu/cpu.c | |
| parent | 40686c394e533fec765fe237936e353c84e73fff (diff) | |
riscv: Add option to support RISC-V privileged spec 1.9
Some older processors (notably the Kendryte K210) use an older version of
the RISC-V privileged specification. The primary changes between the old
and new are in virtual memory, and in the merging of three separate counter
enable CSRs. Using the new CSR on an old processor causes an illegal
instruction exception. This patch adds an option to use the old CSRs
instead of the new one.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/riscv/cpu/cpu.c')
| -rw-r--r-- | arch/riscv/cpu/cpu.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index d75a3f045ae..bbd6c153527 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -91,11 +91,20 @@ int arch_cpu_init_dm(void) * Enable perf counters for cycle, time, * and instret counters only */ +#ifdef CONFIG_RISCV_PRIV_1_9 + csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0)); + csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0)); +#else csr_write(CSR_MCOUNTEREN, GENMASK(2, 0)); +#endif /* Disable paging */ if (supports_extension('s')) +#ifdef CONFIG_RISCV_PRIV_1_9 + csr_read_clear(CSR_MSTATUS, SR_VM); +#else csr_write(CSR_SATP, 0); +#endif } #ifdef CONFIG_SMP |