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authorIlias Apalodimas2021-10-12 00:00:13 +0300
committerTom Rini2021-10-18 13:19:50 -0400
commit2e8d2f88439d7437f04a6af1d206270f9a2240d3 (patch)
tree696b2966fe4df48f0f2a0fcdc76713f4f17644ec /arch/riscv/cpu
parentd990f7d75d3dcf45a9220abc900495f00792f414 (diff)
riscv: Remove OF_PRIOR_STAGE from RISC-V boards
At some point back in 2018 prior_stage_fdt_address and OF_PRIOR_STAGE got introduced, in order to support a DTB handed over by an earlier stage boo loader. However we have another option in the Kconfig (OF_BOARD) which has identical semantics. On RISC-V some of the boards pick up the DTB from a1 and copy it in their private gd_t. Apart from that they copy it to prior_stage_fdt_address, if the Kconfig option is selected, which is unnecessary. So let's switch the config option for those boards to OF_BOARD and define the required board_fdt_blob_setup() for them. Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv/cpu')
-rw-r--r--arch/riscv/cpu/cpu.c3
-rw-r--r--arch/riscv/cpu/start.S5
2 files changed, 0 insertions, 8 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 8e49b6d7364..8d90c5e6b8a 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -17,9 +17,6 @@
* The variables here must be stored in the data section since they are used
* before the bss section is available.
*/
-#ifdef CONFIG_OF_PRIOR_STAGE
-phys_addr_t prior_stage_fdt_address __section(".data");
-#endif
#ifndef CONFIG_XIP
u32 hart_lottery __section(".data") = 0;
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 308b0a97a58..76850ec9be2 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -142,11 +142,6 @@ call_harts_early_init:
bnez tp, secondary_hart_loop
#endif
-#ifdef CONFIG_OF_PRIOR_STAGE
- la t0, prior_stage_fdt_address
- SREG s1, 0(t0)
-#endif
-
jal board_init_f_init_reserve
SREG s1, GD_FIRMWARE_FDT_ADDR(gp)