diff options
| author | Rick Chen | 2019-04-02 15:56:42 +0800 |
|---|---|---|
| committer | Andes | 2019-04-08 09:45:08 +0800 |
| commit | dda00ae4ef357233a72c74e6c02d27b70c844422 (patch) | |
| tree | 53f9e29c4d779504b36dbee95bee7f1f44813f4a /arch/riscv/dts/ae350_32.dts | |
| parent | 8848474c5e9093ac27f6b7cc8be156629c7d0bad (diff) | |
riscv: ax25: Andes specific cache shall only support in M-mode
Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Diffstat (limited to 'arch/riscv/dts/ae350_32.dts')
0 files changed, 0 insertions, 0 deletions