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authorNikita Shubin2022-09-02 11:47:39 +0300
committerLeo Yu-Chi Liang2022-09-26 14:28:43 +0800
commitc2bdf02c9d40da7154fea46b7d10343fe9f14209 (patch)
tree362d3715d67989f0d7208a674422dd9e79681eaf /arch/riscv/lib
parent435596d57f8beedf36b5dc858fe7ba9d6c03334b (diff)
spl: introduce SPL_XIP to config
U-Boot and SPL don't necessary share the same location, so we might end with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory. In case of non XIP boot mode, we rely on such variables as "hart_lottery" and "available_harts_lock" which we use as atomics. The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL, so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes. This adds an option special for SPL to behave it in XIP manner and we don't use hart_lottery and available_harts_lock, during start proccess. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/lib')
-rw-r--r--arch/riscv/lib/asm-offsets.c2
-rw-r--r--arch/riscv/lib/smp.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index f1fe089b3d8..c4f48c83735 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -16,7 +16,7 @@ int main(void)
{
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr));
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
#endif
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index ba992100adf..f8b756291f3 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -45,7 +45,7 @@ static int send_ipi_many(struct ipi_data *ipi, int wait)
continue;
}
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
/* skip if hart is not available */
if (!(gd->arch.available_harts & (1 << reg)))
continue;