diff options
| author | Sagar Shrikant Kadam | 2020-07-29 02:36:13 -0700 |
|---|---|---|
| committer | Andes | 2020-08-04 09:19:41 +0800 |
| commit | d04a46426b92cc175a73e5d2c5220503c428fc6c (patch) | |
| tree | 5b718cefde728238b5e4de22ebe77afb56316421 /arch/riscv | |
| parent | ea4e9570ebed70c785e0076c65c5490cbd2c947b (diff) | |
sifive: reset: add DM based reset driver for SiFive SoC's
PRCI module within SiFive SoC's has register with which we can
reset the sub-systems within the SoC. The resets to DDR and ethernet
sub systems within FU540-C000 SoC are active low, and are hold low
by default on power-up. Currently these are directly asserted within
prci driver via register read/write.
With the DM based reset driver support here, we bind the reset
driver with clock (prci) driver and assert the reset signals of
both sub-system's appropriately.
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/include/asm/arch-fu540/reset.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/arch-fu540/reset.h b/arch/riscv/include/asm/arch-fu540/reset.h new file mode 100644 index 00000000000..e42797a3958 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/reset.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2020 SiFive, Inc. + * + * Author: Sagar Kadam <sagar.kadam@sifive.com> + */ + +#ifndef __RESET_SIFIVE_H +#define __RESET_SIFIVE_H + +int sifive_reset_bind(struct udevice *dev, ulong count); + +#endif |