diff options
| author | Tom Rini | 2024-06-03 18:42:11 -0600 |
|---|---|---|
| committer | Tom Rini | 2024-06-04 08:09:09 -0600 |
| commit | 227be29df37545f74243a98c12a4a33c4160e3cd (patch) | |
| tree | 8a758001963b7b45f869385ef9d00e30faf04bd3 /arch/riscv | |
| parent | 15d0dcc0ec1f424199dff2a3cbe037bc3a7d8749 (diff) | |
| parent | c0ea27bccfb7d2d37fd36806ac2a2f7389099420 (diff) | |
Merge tag 'v2024.07-rc4' into next
Prepare v2024.070-rc4
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/andes/cache.c | 4 | ||||
| -rw-r--r-- | arch/riscv/cpu/start.S | 4 | ||||
| -rw-r--r-- | arch/riscv/include/asm/arch-andes/csr.h | 2 |
3 files changed, 2 insertions, 8 deletions
diff --git a/arch/riscv/cpu/andes/cache.c b/arch/riscv/cpu/andes/cache.c index 7d3df8722dd..bb57498d75a 100644 --- a/arch/riscv/cpu/andes/cache.c +++ b/arch/riscv/cpu/andes/cache.c @@ -43,9 +43,7 @@ static void cache_ops(int (*ops)(struct udevice *dev)) void flush_dcache_all(void) { -#if CONFIG_IS_ENABLED(RISCV_MMODE) - csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); -#endif + csr_write(CSR_UCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); } void flush_dcache_range(unsigned long start, unsigned long end) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index a9e19356928..8e58f641f1b 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -210,10 +210,6 @@ wait_for_gd_init: bnez s2, secondary_hart_loop #endif - /* Enable cache */ - jal icache_enable - jal dcache_enable - #ifdef CONFIG_DEBUG_UART jal debug_uart_init #endif diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index 028fd01c2f3..7d6104a24e5 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -12,7 +12,7 @@ #define CSR_MCACHE_CTL 0x7ca #define CSR_MMISC_CTL 0x7d0 -#define CSR_MCCTLCOMMAND 0x7cc +#define CSR_UCCTLCOMMAND 0x80c /* mcache_ctl register */ |