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authorBin Meng2023-04-13 14:20:06 +0800
committerLeo Yu-Chi Liang2023-04-20 20:45:08 +0800
commit3c09ac2c589fbf4d0976c49956cc9c6d14c33986 (patch)
treed4c4fd63b26c83feb8e6c7c0a357dc68e61d5927 /arch/riscv
parent485f59307957269786384c30e4eee59716727f07 (diff)
riscv: Avoid updating the link register
board_init_r does not return for U-Boot SPL hence there is no need to update the link register when jumping to board_init_r. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/cpu/start.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index c09d1cb4125..8cf25bb14a6 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -250,7 +250,7 @@ spl_secondary_hart_stack_gd_setup:
spl_call_board_init_r:
mv a0, zero
mv a1, zero
- jal board_init_r
+ j board_init_r
#endif
/*