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authorBin Meng2023-04-13 14:20:00 +0800
committerLeo Yu-Chi Liang2023-04-20 20:45:08 +0800
commit883f553e6ba510d4d4ab7d645ff46bc999752e79 (patch)
treeb51304c67f1d58b4254a05741bca83f1e2c7a05b /arch/riscv
parentdb9a7e51bf40e1b60fede560d50afb6c1e830a99 (diff)
riscv: Optimize source end address calculation in start.S
The __bss_start is the source end address hence load its address directly into register 't2' for optimization. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/cpu/start.S4
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 4687bca3c99..3c8344c345b 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -283,9 +283,7 @@ stack_setup:
beq t0, s4, clear_bss /* skip relocation */
mv t1, s4 /* t1 <- scratch for copy_loop */
- la t3, __bss_start
- sub t3, t3, t0 /* t3 <- __bss_start_ofs */
- add t2, t0, t3 /* t2 <- source end address */
+ la t2, __bss_start /* t2 <- source end address */
copy_loop:
LREG t5, 0(t0)