diff options
| author | Leo Yu-Chi Liang | 2022-06-01 10:01:49 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang | 2022-08-11 18:46:07 +0800 |
| commit | f4512618caa0182344aa55c5e15b2a14e28227cd (patch) | |
| tree | 1f8782d42c0530bff0d7df64aa22f62fd6c831c2 /arch/riscv | |
| parent | a5041e33e4f05efec8a412641243c9281cba47e9 (diff) | |
riscv: ae350: Fix XIP config boot failure
The booting flow is SPL -> OpenSBI -> U-Boot.
The boot hart may change after OpenSBI and may not always be hart0,
so wrap the related branch instruction with M-MODE.
Current DTB setup for XIP is not valid.
There is no chance for CONFIG_SYS_FDT_BASE, the DTB address used
in XIP mode, to be returned. Fix this.
Fixes: 2e8d2f88439d ("riscv: Remove OF_PRIOR_STAGE from RISC-V boards")
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/start.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index ac81783a902..b7f21ab63e0 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -140,9 +140,11 @@ call_harts_early_init: * accesses gd). */ mv gp, s0 +#if CONFIG_IS_ENABLED(RISCV_MMODE) bnez tp, secondary_hart_loop #endif - +#endif + mv a0, s0 jal board_init_f_init_reserve |