diff options
| author | Bin Meng | 2021-05-10 17:08:16 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang | 2021-05-14 16:26:20 +0800 |
| commit | ffdc71bc0977c1e6b7b6e6a5a005e1f77213bf21 (patch) | |
| tree | 2bd444c2efe035c3fb12482e7b934d09574c8095 /arch/riscv | |
| parent | cc25f346c9e58f02efb68003d0526825fee265ea (diff) | |
Revert "riscv: cpu: fu740: clear feature disable CSR"
This reverts commit bc8bbb77f74f21582b3bfd790334397757f88575.
This commit breaks U-Boot booting on SiFive Unleashed board, as
there is no such CSR on U54 core.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/fu540/spl.c | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c index 1740ef98b6b..45657b79096 100644 --- a/arch/riscv/cpu/fu540/spl.c +++ b/arch/riscv/cpu/fu540/spl.c @@ -6,9 +6,6 @@ #include <dm.h> #include <log.h> -#include <asm/csr.h> - -#define CSR_U74_FEATURE_DISABLE 0x7c1 int spl_soc_init(void) { @@ -24,15 +21,3 @@ int spl_soc_init(void) return 0; } - -void harts_early_init(void) -{ - /* - * Feature Disable CSR - * - * Clear feature disable CSR to '0' to turn on all features for - * each core. This operation must be in M-mode. - */ - if (CONFIG_IS_ENABLED(RISCV_MMODE)) - csr_write(CSR_U74_FEATURE_DISABLE, 0); -} |