diff options
| author | Bin Meng | 2017-08-15 22:42:01 -0700 |
|---|---|---|
| committer | Bin Meng | 2017-09-16 14:57:44 +0800 |
| commit | 507f1024b8f2659e78324ce459f5965de4232c24 (patch) | |
| tree | b7f6e9f4db042904d3493d3116e9a2f2f169493e /arch/x86/cpu/braswell/fsp_configs.c | |
| parent | fffad9264aa63a2f8da7d15d27d9a7c03a5ff4ec (diff) | |
x86: braswell: Disable PUNIT power configuration for B0 stepping
FSP's built-in UPD configuration enables PUNIT power configuration,
but on B0 stepping, this causes CPU hangs in fsp_init(). Disable it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu/braswell/fsp_configs.c')
| -rw-r--r-- | arch/x86/cpu/braswell/fsp_configs.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/x86/cpu/braswell/fsp_configs.c b/arch/x86/cpu/braswell/fsp_configs.c index d9845191d32..249f851265a 100644 --- a/arch/x86/cpu/braswell/fsp_configs.c +++ b/arch/x86/cpu/braswell/fsp_configs.c @@ -139,6 +139,12 @@ void update_fsp_configs(struct fsp_config_data *config, #endif update_fsp_gpio_configs(&silicon_upd->gpio_familiy_ptr, &silicon_upd->gpio_pad_ptr); + /* + * For Braswell B0 stepping, disable_punit_pwr_config must be set to 1 + * otherwise it just hangs in fsp_init(). + */ + if (gd->arch.x86_mask == 2) + silicon_upd->disable_punit_pwr_config = 1; silicon_upd->emmc_mode = fdtdec_get_int(blob, node, "fsp,emmc-mode", EMMC_MODE_PCI); silicon_upd->sata_speed = fdtdec_get_int(blob, node, |