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authorSimon Glass2016-01-18 20:19:21 -0700
committerBin Meng2016-01-24 12:07:17 +0800
commitf2b85ab5e6a91e29c1d64304be371753d75ed172 (patch)
treec7e65743fd66f6a06f425bd8bf7bc643f807eefe /arch/x86/cpu/irq.c
parentfffe25db04b428f34b72264ff50c40f395fcd936 (diff)
dm: x86: spi: Convert ICH SPI driver to driver model PCI API
At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/irq.c')
-rw-r--r--arch/x86/cpu/irq.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 35b29f69d84..205405b95fe 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -97,6 +97,7 @@ static int create_pirq_routing_table(void)
struct irq_routing_table *rt;
struct irq_info *slot, *slot_base;
int irq_entries = 0;
+ int parent;
int i;
int ret;
@@ -106,7 +107,11 @@ static int create_pirq_routing_table(void)
return -EINVAL;
}
- ret = fdtdec_get_pci_addr(blob, node, FDT_PCI_SPACE_CONFIG,
+ /* TODO(sjg@chromium.org): Drop this when PIRQ is a driver */
+ parent = fdt_parent_offset(blob, node);
+ if (parent < 0)
+ return -EINVAL;
+ ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG,
"reg", &addr);
if (ret)
return ret;