diff options
| author | Bin Meng | 2015-10-11 21:37:44 -0700 |
|---|---|---|
| committer | Simon Glass | 2015-10-21 07:46:27 -0600 |
| commit | 638a05894169b07ea8f6d21b6925ca353ea6ebb7 (patch) | |
| tree | 68308063e00f4b803a07b9f55d56b2973edc2c7b /arch/x86/dts | |
| parent | 8b185041a9f4c30dc5edb1e04c0834e931b8633f (diff) | |
x86: Enable mrc cache for bayleybay and minnowmax
Now that we have added MRC cache for Intel FSP and BayTrail codes,
enable it for all BayTrail boards (Bayley Bay and Minnow Max).
Note it turns out that FSP for Intel Atom E6xx does not produce
the HOB for NV storage, so we don't have such functionality on
Intel Crown Bay board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/dts')
| -rw-r--r-- | arch/x86/dts/bayleybay.dts | 6 | ||||
| -rw-r--r-- | arch/x86/dts/minnowmax.dts | 6 |
2 files changed, 12 insertions, 0 deletions
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index d646987ff88..52d0999f19f 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -68,9 +68,15 @@ #size-cells = <0>; compatible = "intel,ich-spi"; spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; compatible = "winbond,w25q64dw", "spi-flash"; memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x006e0000 0x00010000>; + }; }; }; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index e917f0f55b0..b03f9878dda 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -273,9 +273,15 @@ #size-cells = <0>; compatible = "intel,ich-spi"; spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; compatible = "stmicro,n25q064a", "spi-flash"; memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x006f0000 0x00010000>; + }; }; }; |