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authorBin Meng2015-06-23 12:18:50 +0800
committerSimon Glass2015-07-14 18:03:17 -0600
commita2d73fdba638233253c14b31f3befb9099d76774 (patch)
treeb1c935675f22ff5d2b07de4be7ce7429627b608e /arch/x86/include
parent3d232878289bf59e83c6b152407a01f6e0fb790b (diff)
x86: Remove inline for lapic access routines
Remove inline for lapic access routines and expose lapic_read() & lapic_write() as APIs to read/write lapic registers. Also move stop_this_cpu() to mp_init.c as it has nothing to do with lapic. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include')
-rw-r--r--arch/x86/include/asm/lapic.h134
1 files changed, 10 insertions, 124 deletions
diff --git a/arch/x86/include/asm/lapic.h b/arch/x86/include/asm/lapic.h
index f60974a878a..bc2b2d15205 100644
--- a/arch/x86/include/asm/lapic.h
+++ b/arch/x86/include/asm/lapic.h
@@ -9,11 +9,6 @@
#ifndef _ARCH_ASM_LAPIC_H
#define _ARCH_ASM_LAPIC_H
-#include <asm/io.h>
-#include <asm/msr.h>
-#include <asm/msr-index.h>
-#include <asm/processor.h>
-
#define LAPIC_DEFAULT_BASE 0xfee00000
#define LAPIC_ID 0x020
@@ -66,126 +61,17 @@
#define LAPIC_DELIVERY_MODE_NMI (4 << 8)
#define LAPIC_DELIVERY_MODE_EXTINT (7 << 8)
-static inline __attribute__((always_inline))
- unsigned long lapic_read(unsigned long reg)
-{
- return readl(LAPIC_DEFAULT_BASE + reg);
-}
-
-static inline __attribute__((always_inline))
- void lapic_write(unsigned long reg, unsigned long val)
-{
- writel(val, LAPIC_DEFAULT_BASE + reg);
-}
-
-static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
-{
- do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY);
-}
-
-static inline void enable_lapic(void)
-{
- msr_t msr;
-
- msr = msr_read(MSR_IA32_APICBASE);
- msr.hi &= 0xffffff00;
- msr.lo |= MSR_IA32_APICBASE_ENABLE;
- msr.lo &= ~MSR_IA32_APICBASE_BASE;
- msr.lo |= LAPIC_DEFAULT_BASE;
- msr_write(MSR_IA32_APICBASE, msr);
-}
-
-static inline void disable_lapic(void)
-{
- msr_t msr;
-
- msr = msr_read(MSR_IA32_APICBASE);
- msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
- msr_write(MSR_IA32_APICBASE, msr);
-}
-
-static inline __attribute__((always_inline)) unsigned long lapicid(void)
-{
- return lapic_read(LAPIC_ID) >> 24;
-}
-
-static inline __attribute__((always_inline)) void stop_this_cpu(void)
-{
- /* Called by an AP when it is ready to halt and wait for a new task */
- for (;;)
- cpu_hlt();
-}
-
-#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
- sizeof(*(ptr))))
-
-struct __xchg_dummy { unsigned long a[100]; };
-#define __xg(x) ((struct __xchg_dummy *)(x))
+unsigned long lapic_read(unsigned long reg);
-/*
- * Note: no "lock" prefix even on SMP. xchg always implies lock anyway.
- *
- * Note 2: xchg has side effect, so that attribute volatile is necessary,
- * but generally the primitive is invalid, *ptr is output argument.
- */
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
- int size)
-{
- switch (size) {
- case 1:
- __asm__ __volatile__("xchgb %b0,%1"
- : "=q" (x)
- : "m" (*__xg(ptr)), "0" (x)
- : "memory");
- break;
- case 2:
- __asm__ __volatile__("xchgw %w0,%1"
- : "=r" (x)
- : "m" (*__xg(ptr)), "0" (x)
- : "memory");
- break;
- case 4:
- __asm__ __volatile__("xchgl %0,%1"
- : "=r" (x)
- : "m" (*__xg(ptr)), "0" (x)
- : "memory");
- break;
- }
-
- return x;
-}
-
-static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
-{
- (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
-}
-
-#define lapic_read_around(x) lapic_read(x)
-#define lapic_write_around(x, y) lapic_write_atomic((x), (y))
-
-static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
-{
- int timeout;
- unsigned long status;
- int result;
-
- lapic_wait_icr_idle();
- lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
- lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
-
- timeout = 0;
- do {
- status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
- } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
-
- result = -1;
- if (status == LAPIC_ICR_RR_VALID) {
- *pvalue = lapic_read(LAPIC_RRR);
- result = 0;
- }
-
- return result;
-}
+void lapic_write(unsigned long reg, unsigned long v);
+
+void enable_lapic(void);
+
+void disable_lapic(void);
+
+unsigned long lapicid(void);
+
+int lapic_remote_read(int apicid, int reg, unsigned long *pvalue);
void lapic_setup(void);