diff options
| author | Simon Glass | 2020-11-04 09:57:35 -0700 |
|---|---|---|
| committer | Bin Meng | 2020-11-06 09:51:31 +0800 |
| commit | 96d0aa91430b885eed2a01f0b9edc0107687ab06 (patch) | |
| tree | d74bac4abec8b51f73497b7faf899a26d4dfacf8 /arch/x86 | |
| parent | 08059c9c02b1e87add0f2409d15ab5cdc745b6fd (diff) | |
x86: Use CONFIG_CHROMEOS_VBOOT for verified boot
At present CONFIG_CHROMEOS is used to determine whether verified boot is
in use. The code to implement that is not in U-Boot mainline.
However, it is useful to be able to boot a Chromebook in developer mode
in U-Boot mainline without needing the verified boot code.
To allow this, use CONFIG_CHROMEOS_VBOOT to indicate that verified boot
should be used, and CONFIG_CHROMEOS to indicate that the board supports
Chrome OS. That allows us to define CONFIG_CHROMEOS on coral.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/cpu/apollolake/acpi.c | 3 | ||||
| -rw-r--r-- | arch/x86/dts/chromebook_coral.dts | 2 | ||||
| -rw-r--r-- | arch/x86/dts/chromebook_samus.dts | 2 | ||||
| -rw-r--r-- | arch/x86/include/asm/intel_gnvs.h | 3 | ||||
| -rw-r--r-- | arch/x86/lib/tpl.c | 2 |
5 files changed, 5 insertions, 7 deletions
diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c index 69b544f0d98..5af8a181b1e 100644 --- a/arch/x86/cpu/apollolake/acpi.c +++ b/arch/x86/cpu/apollolake/acpi.c @@ -75,7 +75,8 @@ int acpi_create_gnvs(struct acpi_global_nvs *gnvs) /* TODO(sjg@chromium.org): Add the console log to gnvs->cbmc */ -#ifdef CONFIG_CHROMEOS +/* Disable this code until a later patch */ +#if 0 /* Initialise Verified Boot data */ chromeos_init_acpi(&gnvs->chromeos); gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 92f70b13dd7..43f4b33da1b 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -9,7 +9,7 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -#ifdef CONFIG_CHROMEOS +#ifdef CONFIG_CHROMEOS_VBOOT #include "chromeos-x86.dtsi" #include "flashmap-x86-ro.dtsi" #include "flashmap-16mb-rw.dtsi" diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index 772ea5c91be..d8e04a66985 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -9,7 +9,7 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -#ifdef CONFIG_CHROMEOS +#ifdef CONFIG_CHROMEOS_VBOOT #include "chromeos-x86.dtsi" #include "flashmap-x86-ro.dtsi" #include "flashmap-8mb-rw.dtsi" diff --git a/arch/x86/include/asm/intel_gnvs.h b/arch/x86/include/asm/intel_gnvs.h index 632307427cd..7f9f101371c 100644 --- a/arch/x86/include/asm/intel_gnvs.h +++ b/arch/x86/include/asm/intel_gnvs.h @@ -85,9 +85,6 @@ struct __packed acpi_global_nvs { u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */ #endif }; - -#ifdef CONFIG_CHROMEOS check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); -#endif #endif /* _INTEL_GNVS_H_ */ diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index 6f7eb43a172..15b0212d190 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -75,7 +75,7 @@ void board_init_f_r(void) u32 spl_boot_device(void) { - return IS_ENABLED(CONFIG_CHROMEOS) ? BOOT_DEVICE_CROS_VBOOT : + return IS_ENABLED(CONFIG_CHROMEOS_VBOOT) ? BOOT_DEVICE_CROS_VBOOT : BOOT_DEVICE_SPI_MMAP; } |