diff options
| author | Marek Vasut | 2015-12-20 04:00:09 +0100 |
|---|---|---|
| committer | Marek Vasut | 2015-12-22 04:42:27 +0100 |
| commit | 07806977878130dd27dfc926ef7002041f6cf288 (patch) | |
| tree | 126641ee05b663ad61f9c2eb7d3c94ebe891450f /arch | |
| parent | 3721208fa7fdb2af6ac13300d5d81433742c6ba1 (diff) | |
arm: socfpga: Actually enable L2 cache
The L2 cache was never enabled in the v7_outer_cache_enable(), fix
this and enable the L2 cache.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-socfpga/misc.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index b110f5bb42b..a54d2b9faaa 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -54,14 +54,23 @@ void enable_caches(void) void v7_outer_cache_enable(void) { - /* disable the L2 cache */ - writel(0, &pl310->pl310_ctrl); + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); /* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | L310_AUX_CTRL_INST_PREFETCH_MASK | L310_SHARED_ATT_OVERRIDE_ENABLE); + + /* Enable the L2 cache */ + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + +void v7_outer_cache_disable(void) +{ + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } /* |