diff options
author | Álvaro Fernández Rojas | 2018-01-23 17:14:59 +0100 |
---|---|---|
committer | Jagan Teki | 2018-01-24 12:03:43 +0530 |
commit | 0adfb199cead1c170a1d4cd4d3b90f4a3cd8ef52 (patch) | |
tree | 1656659535d8a334e829f21a12ece91f0f4f839f /arch | |
parent | 5ac07d2969e7f1ea2582f97ccacbe9ad9c9d62fc (diff) |
mips: bmips: add bcm63xx-spi driver support for BCM6338
This driver manages the SPI controller present on this SoC.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/mips/dts/brcm,bcm6338.dtsi | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/mips/dts/brcm,bcm6338.dtsi b/arch/mips/dts/brcm,bcm6338.dtsi index eb51a4372bd..0cab44cb8d5 100644 --- a/arch/mips/dts/brcm,bcm6338.dtsi +++ b/arch/mips/dts/brcm,bcm6338.dtsi @@ -12,6 +12,10 @@ / { compatible = "brcm,bcm6338"; + aliases { + spi0 = &spi; + }; + cpus { reg = <0xfffe0000 0x4>; #address-cells = <1>; @@ -109,6 +113,19 @@ status = "disabled"; }; + spi: spi@fffe0c00 { + compatible = "brcm,bcm6348-spi"; + reg = <0xfffe0c00 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6338_CLK_SPI>; + resets = <&periph_rst BCM6338_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <4>; + + status = "disabled"; + }; + memory-controller@fffe3100 { compatible = "brcm,bcm6338-mc"; reg = <0xfffe3100 0x38>; |