diff options
| author | Marek Vasut | 2023-03-06 15:53:47 +0100 |
|---|---|---|
| committer | Stefano Babic | 2023-03-30 13:47:03 +0200 |
| commit | 158456089c02ef7564decea6cff2c5b285fe66d7 (patch) | |
| tree | f1a992c8c51bb07e33f245cac0d9625a4dda06a7 /arch | |
| parent | a79de0808a8dc738ec2076ad47d431c64452111e (diff) | |
net: dwc_eth_qos: Add DM CLK support for i.MX8M Plus
The DWMAC clock in i.MX8M Plus were so far configured via ad-hoc
architecture code. Replace that with DM clock instead. This way,
the driver claims all its required clock, enables and disables
them, and even gets the CSR clock rate and sets the TX clock rate,
without any need of architecture specific register fiddling. Drop
the architecture specific code while at it too.
The adjustment here is modeled after STM32MP15xx clock handling
in this driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/imx8m/clock_imx8mm.c | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 64ad57e9b39..494bfbedc8c 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -872,47 +872,6 @@ int set_clk_eqos(enum enet_freq type) return 0; } - -int imx_eqos_txclk_set_rate(ulong rate) -{ - u32 val; - u32 eqos_post_div; - - /* disable the clock first */ - clock_enable(CCGR_QOS_ETHENET, 0); - clock_enable(CCGR_SDMA2, 0); - - switch (rate) { - case 125000000: - eqos_post_div = 1; - break; - case 25000000: - eqos_post_div = 125000000 / 25000000; - break; - case 2500000: - eqos_post_div = 125000000 / 2500000; - break; - default: - return -EINVAL; - } - - clock_get_target_val(ENET_QOS_CLK_ROOT, &val); - val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK); - val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | - CLK_ROOT_POST_DIV(eqos_post_div - 1); - clock_set_target_val(ENET_QOS_CLK_ROOT, val); - - /* enable clock */ - clock_enable(CCGR_QOS_ETHENET, 1); - clock_enable(CCGR_SDMA2, 1); - - return 0; -} - -u32 imx_get_eqos_csr_clk(void) -{ - return get_root_clk(ENET_AXI_CLK_ROOT); -} #endif #ifdef CONFIG_FEC_MXC |