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authorTom Rini2018-10-05 21:17:21 -0400
committerTom Rini2018-10-05 21:17:21 -0400
commit1b484736ce47cb220cb523f00ebe77025cab219f (patch)
treee82ad573068ff2f6be390bacfc2d43c6ed6f8218 /arch
parenta4b38fca7e83f0556c0afc96492741e4464444df (diff)
parent8be11fb3c1d8d89ff6b60bd3937efcea2dc9c91d (diff)
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-socfpga/include/mach/reset_manager_s10.h2
-rw-r--r--arch/arm/mach-socfpga/misc_s10.c5
-rw-r--r--arch/arm/mach-socfpga/reset_manager_s10.c35
3 files changed, 3 insertions, 39 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
index 6182d5fa3f4..31b73edabe2 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -108,8 +108,6 @@ struct socfpga_reset_manager {
#define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25)
#define RSTMGR_SDR RSTMGR_DEFINE(3, 6)
-void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state);
-
/* Create a human-readable reference to SoCFPGA reset. */
#define SOCFPGA_RESET(_name) RSTMGR_##_name
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index 918baac5025..e599362f145 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -36,7 +36,8 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
if (!phymode)
return -EINVAL;
- if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii"))
+ if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") ||
+ !strcmp(phymode, "sgmii"))
modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
else if (!strcmp(phymode, "rgmii"))
modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
@@ -58,7 +59,7 @@ static int socfpga_set_phymode(void)
struct fdtdec_phandle_args args;
const char *phy_mode;
u32 gmac_index;
- int nodes[2]; /* Max. 3 GMACs */
+ int nodes[3]; /* Max. 3 GMACs */
int ret, count;
int i, node;
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index 5cc83367407..f176c384951 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -93,41 +93,6 @@ void socfpga_bridges_reset(int enable)
}
}
-/* of_reset_id: emac reset id
- * state: 0 - disable reset, !0 - enable reset
- */
-void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state)
-{
- u32 reset_emac;
- u32 reset_emacocp;
-
- /* hardcode this now */
- switch (of_reset_id) {
- case EMAC0_RESET:
- reset_emac = SOCFPGA_RESET(EMAC0);
- reset_emacocp = SOCFPGA_RESET(EMAC0_OCP);
- break;
- case EMAC1_RESET:
- reset_emac = SOCFPGA_RESET(EMAC1);
- reset_emacocp = SOCFPGA_RESET(EMAC1_OCP);
- break;
- case EMAC2_RESET:
- reset_emac = SOCFPGA_RESET(EMAC2);
- reset_emacocp = SOCFPGA_RESET(EMAC2_OCP);
- break;
- default:
- printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
- hang();
- break;
- }
-
- /* Reset ECC OCP first */
- socfpga_per_reset(reset_emacocp, state);
-
- /* Release the EMAC controller from reset */
- socfpga_per_reset(reset_emac, state);
-}
-
/*
* Release peripherals from reset based on handoff
*/