Merge tag 'video-20240421' of https://source.denx.de/u-boot/custodians/u-boot-video

CI: https://source.denx.de/u-boot/custodians/u-boot-video/-/pipelines/20466

- simple_panel: support timing parsing from EDID
- dw_hdmi: fix gcc-14 compiler warnings
- dw_hdmi: support vendor PHY for HDMI
- rockchip: add Rockchip INNO HDMI PHY driver
- rockchip: RK3328 HDMI and VOP support
- evb-rk3328: enable vidconsole support
- Tegra DC and DSI improvements and Tegra 114 support
- add LG LG070WX3 MIPI DSI panel driver
- add Samsung LTL106HL02 MIPI DSI panel driver
- add Toshiba TC358768 RGB to DSI bridge support
- add basic support for the Parade DP501 transmitter
- Tegra 3 panel and bridge driver improvements
- simplefb: modernise DT parsing
- fdt_simplefb: Enumerate framebuffer info from video handoff
- preserve framebuffer if SPL is passing video hand-off
- fdt_support: allow reserving FB region without simplefb

12 files changed, 77 insertions, 284 deletions

diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index e0c6aee58ab..7c5067cf002 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -130,6 +130,10 @@
 	bootph-all;
 };
 
+&vop {
+	bootph-all;
+};
+
 #ifdef CONFIG_ROCKCHIP_SPI_IMAGE
 &binman {
 	simple-bin-spi {
diff --git a/arch/arm/dts/tegra114-u-boot.dtsi b/arch/arm/dts/tegra114-u-boot.dtsi
index 7c119725528..6a02714a258 100644
--- a/arch/arm/dts/tegra114-u-boot.dtsi
+++ b/arch/arm/dts/tegra114-u-boot.dtsi
@@ -1,3 +1,16 @@
 #include <config.h>
 
 #include "tegra-u-boot.dtsi"
+
+/ {
+	host1x@50000000 {
+		bootph-all;
+		dc@54200000 {
+			bootph-all;
+		};
+
+		dc@54240000 {
+			bootph-all;
+		};
+	};
+};
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index 68ee7f31656..250d692f6bf 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -42,7 +42,7 @@
 		};
 
 		dc@54200000 {
-			compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
+			compatible = "nvidia,tegra114-dc";
 			reg = <0x54200000 0x00040000>;
 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA114_CLK_DISP1>,
@@ -61,7 +61,7 @@
 		};
 
 		dc@54240000 {
-			compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
+			compatible = "nvidia,tegra114-dc";
 			reg = <0x54240000 0x00040000>;
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA114_CLK_DISP2>,
diff --git a/arch/arm/dts/tegra30-u-boot.dtsi b/arch/arm/dts/tegra30-u-boot.dtsi
index 3038227dbed..6a02714a258 100644
--- a/arch/arm/dts/tegra30-u-boot.dtsi
+++ b/arch/arm/dts/tegra30-u-boot.dtsi
@@ -8,5 +8,9 @@
 		dc@54200000 {
 			bootph-all;
 		};
+
+		dc@54240000 {
+			bootph-all;
+		};
 	};
 };
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index f198bc0edbe..1177e2ab1f4 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -158,7 +158,7 @@
 		};
 
 		dc@54200000 {
-			compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
+			compatible = "nvidia,tegra30-dc";
 			reg = <0x54200000 0x00040000>;
 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_DISP1>,
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
index 226744d67d9..4ad1d33e056 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
@@ -62,6 +62,40 @@ check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
 enum apll_frequencies {
 	APLL_816_MHZ,
 	APLL_600_MHZ,
+
+	/* CRU_CLK_SEL37_CON */
+	ACLK_VIO_PLL_SEL_CPLL		= 0,
+	ACLK_VIO_PLL_SEL_GPLL		= 1,
+	ACLK_VIO_PLL_SEL_HDMIPHY	= 2,
+	ACLK_VIO_PLL_SEL_USB480M	= 3,
+	ACLK_VIO_PLL_SEL_SHIFT		= 6,
+	ACLK_VIO_PLL_SEL_MASK		= 3 << ACLK_VIO_PLL_SEL_SHIFT,
+	ACLK_VIO_DIV_CON_SHIFT		= 0,
+	ACLK_VIO_DIV_CON_MASK		= 0x1f << ACLK_VIO_DIV_CON_SHIFT,
+	HCLK_VIO_DIV_CON_SHIFT		= 8,
+	HCLK_VIO_DIV_CON_MASK		= 0x1f << HCLK_VIO_DIV_CON_SHIFT,
+
+	/* CRU_CLK_SEL39_CON */
+	ACLK_VOP_PLL_SEL_CPLL		= 0,
+	ACLK_VOP_PLL_SEL_GPLL		= 1,
+	ACLK_VOP_PLL_SEL_HDMIPHY	= 2,
+	ACLK_VOP_PLL_SEL_USB480M	= 3,
+	ACLK_VOP_PLL_SEL_SHIFT		= 6,
+	ACLK_VOP_PLL_SEL_MASK		= 3 << ACLK_VOP_PLL_SEL_SHIFT,
+	ACLK_VOP_DIV_CON_SHIFT		= 0,
+	ACLK_VOP_DIV_CON_MASK		= 0x1f << ACLK_VOP_DIV_CON_SHIFT,
+
+	/* CRU_CLK_SEL40_CON */
+	DCLK_LCDC_PLL_SEL_GPLL		= 0,
+	DCLK_LCDC_PLL_SEL_CPLL		= 1,
+	DCLK_LCDC_PLL_SEL_SHIFT		= 0,
+	DCLK_LCDC_PLL_SEL_MASK		= 1 << DCLK_LCDC_PLL_SEL_SHIFT,
+	DCLK_LCDC_SEL_HDMIPHY		= 0,
+	DCLK_LCDC_SEL_PLL		= 1,
+	DCLK_LCDC_SEL_SHIFT		= 1,
+	DCLK_LCDC_SEL_MASK		= 1 << DCLK_LCDC_SEL_SHIFT,
+	DCLK_LCDC_DIV_CON_SHIFT		= 8,
+	DCLK_LCDC_DIV_CON_MASK		= 0xFf << DCLK_LCDC_DIV_CON_SHIFT,
 };
 
 void rk3328_configure_cpu(struct rk3328_cru *cru,
diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h
index 7613d84f221..ca3718411ab 100644
--- a/arch/arm/include/asm/arch-tegra/dc.h
+++ b/arch/arm/include/asm/arch-tegra/dc.h
@@ -443,6 +443,11 @@ enum win_color_depth_id {
 #define	WINDOW_D_SELECT		BIT(7)
 #define	WINDOW_H_SELECT		BIT(8)
 
+/* DC_COM_PIN_OUTPUT_POLARITY1 0x307 */
+#define LHS_OUTPUT_POLARITY_LOW		BIT(30)
+#define LVS_OUTPUT_POLARITY_LOW		BIT(28)
+#define LSC0_OUTPUT_POLARITY_LOW	BIT(24)
+
 /* DC_DISP_DISP_WIN_OPTIONS 0x402 */
 #define	CURSOR_ENABLE		BIT(16)
 #define	SOR_ENABLE		BIT(25)
@@ -569,12 +574,4 @@ enum {
 #define DC_N_WINDOWS			5
 #define DC_REG_SAVE_SPACE		(DC_N_WINDOWS + 5)
 
-#define TEGRA_DSI_A		"dsi@54300000"
-#define TEGRA_DSI_B		"dsi@54400000"
-
-struct tegra_dc_plat {
-	struct udevice *dev;		/* Display controller device */
-	struct dc_ctlr *dc;		/* Display controller regmap */
-};
-
 #endif /* __ASM_ARCH_TEGRA_DC_H */
diff --git a/arch/arm/include/asm/arch-tegra114/pwm.h b/arch/arm/include/asm/arch-tegra114/pwm.h
new file mode 100644
index 00000000000..af391518035
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/pwm.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Tegra pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_ARCH_TEGRA114_PWM_H
+#define __ASM_ARCH_TEGRA114_PWM_H
+
+#include <asm/arch-tegra/pwm.h>
+
+#endif	/* __ASM_ARCH_TEGRA114_PWM_H */
diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra20/display.h
deleted file mode 100644
index e7b3cffd466..00000000000
--- a/arch/arm/include/asm/arch-tegra20/display.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  (C) Copyright 2010
- *  NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
-#define __ASM_ARCH_TEGRA_DISPLAY_H
-
-#include <asm/arch-tegra/dc.h>
-
-/* This holds information about a window which can be displayed */
-struct disp_ctl_win {
-	enum win_color_depth_id fmt;	/* Color depth/format */
-	unsigned	bpp;		/* Bits per pixel */
-	phys_addr_t	phys_addr;	/* Physical address in memory */
-	unsigned	x;		/* Horizontal address offset (bytes) */
-	unsigned	y;		/* Veritical address offset (bytes) */
-	unsigned	w;		/* Width of source window */
-	unsigned	h;		/* Height of source window */
-	unsigned	stride;		/* Number of bytes per line */
-	unsigned	out_x;		/* Left edge of output window (col) */
-	unsigned	out_y;		/* Top edge of output window (row) */
-	unsigned	out_w;		/* Width of output window in pixels */
-	unsigned	out_h;		/* Height of output window in pixels */
-};
-
-#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
diff --git a/arch/arm/include/asm/arch-tegra30/display.h b/arch/arm/include/asm/arch-tegra30/display.h
deleted file mode 100644
index 9411525799d..00000000000
--- a/arch/arm/include/asm/arch-tegra30/display.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  (C) Copyright 2010
- *  NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
-#define __ASM_ARCH_TEGRA_DISPLAY_H
-
-#include <asm/arch-tegra/dc.h>
-
-/* This holds information about a window which can be displayed */
-struct disp_ctl_win {
-	enum win_color_depth_id fmt;	/* Color depth/format */
-	unsigned int	bpp;		/* Bits per pixel */
-	phys_addr_t	phys_addr;	/* Physical address in memory */
-	unsigned int	x;		/* Horizontal address offset (bytes) */
-	unsigned int	y;		/* Veritical address offset (bytes) */
-	unsigned int	w;		/* Width of source window */
-	unsigned int	h;		/* Height of source window */
-	unsigned int	stride;		/* Number of bytes per line */
-	unsigned int	out_x;		/* Left edge of output window (col) */
-	unsigned int	out_y;		/* Top edge of output window (row) */
-	unsigned int	out_w;		/* Width of output window in pixels */
-	unsigned int	out_h;		/* Height of output window in pixels */
-};
-
-#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
diff --git a/arch/arm/include/asm/arch-tegra30/dsi.h b/arch/arm/include/asm/arch-tegra30/dsi.h
deleted file mode 100644
index 7ade132613f..00000000000
--- a/arch/arm/include/asm/arch-tegra30/dsi.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  (C) Copyright 2010
- *  NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef __ASM_ARCH_TEGRA_DSI_H
-#define __ASM_ARCH_TEGRA_DSI_H
-
-#ifndef __ASSEMBLY__
-#include <linux/bitops.h>
-#endif
-
-/* Register definitions for the Tegra display serial interface */
-
-/* DSI syncpoint register 0x000 ~ 0x002 */
-struct dsi_syncpt_reg {
-	/* Address 0x000 ~ 0x002 */
-	uint incr_syncpt;		/* _INCR_SYNCPT_0 */
-	uint incr_syncpt_ctrl;		/* _INCR_SYNCPT_CNTRL_0 */
-	uint incr_syncpt_err;		/* _INCR_SYNCPT_ERROR_0 */
-};
-
-/* DSI misc register 0x008 ~ 0x015 */
-struct dsi_misc_reg {
-	/* Address 0x008 ~ 0x015 */
-	uint ctxsw;			/* _CTXSW_0 */
-	uint dsi_rd_data;		/* _DSI_RD_DATA_0 */
-	uint dsi_wr_data;		/* _DSI_WR_DATA_0 */
-	uint dsi_pwr_ctrl;		/* _DSI_POWER_CONTROL_0 */
-	uint int_enable;		/* _INT_ENABLE_0 */
-	uint int_status;		/* _INT_STATUS_0 */
-	uint int_mask;			/* _INT_MASK_0 */
-	uint host_dsi_ctrl;		/* _HOST_DSI_CONTROL_0 */
-	uint dsi_ctrl;			/* _DSI_CONTROL_0 */
-	uint dsi_sol_delay;		/* _DSI_SOL_DELAY_0 */
-	uint dsi_max_threshold;		/* _DSI_MAX_THRESHOLD_0 */
-	uint dsi_trigger;		/* _DSI_TRIGGER_0 */
-	uint dsi_tx_crc;		/* _DSI_TX_CRC_0 */
-	uint dsi_status;		/* _DSI_STATUS_0 */
-};
-
-/* DSI init sequence register 0x01a ~ 0x022 */
-struct dsi_init_seq_reg {
-	/* Address 0x01a ~ 0x022 */
-	uint dsi_init_seq_ctrl;		/* _DSI_INIT_SEQ_CONTROL_0 */
-	uint dsi_init_seq_data_0;	/* _DSI_INIT_SEQ_DATA_0_0 */
-	uint dsi_init_seq_data_1;	/* _DSI_INIT_SEQ_DATA_1_0 */
-	uint dsi_init_seq_data_2;	/* _DSI_INIT_SEQ_DATA_2_0 */
-	uint dsi_init_seq_data_3;	/* _DSI_INIT_SEQ_DATA_3_0 */
-	uint dsi_init_seq_data_4;	/* _DSI_INIT_SEQ_DATA_4_0 */
-	uint dsi_init_seq_data_5;	/* _DSI_INIT_SEQ_DATA_5_0 */
-	uint dsi_init_seq_data_6;	/* _DSI_INIT_SEQ_DATA_6_0 */
-	uint dsi_init_seq_data_7;	/* _DSI_INIT_SEQ_DATA_7_0 */
-};
-
-/* DSI packet sequence register 0x023 ~ 0x02e */
-struct dsi_pkt_seq_reg {
-	/* Address 0x023 ~ 0x02e */
-	uint dsi_pkt_seq_0_lo;		/* _DSI_PKT_SEQ_0_LO_0 */
-	uint dsi_pkt_seq_0_hi;		/* _DSI_PKT_SEQ_0_HI_0 */
-	uint dsi_pkt_seq_1_lo;		/* _DSI_PKT_SEQ_1_LO_0 */
-	uint dsi_pkt_seq_1_hi;		/* _DSI_PKT_SEQ_1_HI_0 */
-	uint dsi_pkt_seq_2_lo;		/* _DSI_PKT_SEQ_2_LO_0 */
-	uint dsi_pkt_seq_2_hi;		/* _DSI_PKT_SEQ_2_HI_0 */
-	uint dsi_pkt_seq_3_lo;		/* _DSI_PKT_SEQ_3_LO_0 */
-	uint dsi_pkt_seq_3_hi;		/* _DSI_PKT_SEQ_3_HI_0 */
-	uint dsi_pkt_seq_4_lo;		/* _DSI_PKT_SEQ_4_LO_0 */
-	uint dsi_pkt_seq_4_hi;		/* _DSI_PKT_SEQ_4_HI_0 */
-	uint dsi_pkt_seq_5_lo;		/* _DSI_PKT_SEQ_5_LO_0 */
-	uint dsi_pkt_seq_5_hi;		/* _DSI_PKT_SEQ_5_HI_0 */
-};
-
-/* DSI packet length register 0x033 ~ 0x037 */
-struct dsi_pkt_len_reg {
-	/* Address 0x033 ~ 0x037 */
-	uint dsi_dcs_cmds;		/* _DSI_DCS_CMDS_0 */
-	uint dsi_pkt_len_0_1;		/* _DSI_PKT_LEN_0_1_0 */
-	uint dsi_pkt_len_2_3;		/* _DSI_PKT_LEN_2_3_0 */
-	uint dsi_pkt_len_4_5;		/* _DSI_PKT_LEN_4_5_0 */
-	uint dsi_pkt_len_6_7;		/* _DSI_PKT_LEN_6_7_0 */
-};
-
-/* DSI PHY timing register 0x03c ~ 0x03f */
-struct dsi_timing_reg {
-	/* Address 0x03c ~ 0x03f */
-	uint dsi_phy_timing_0;		/* _DSI_PHY_TIMING_0_0 */
-	uint dsi_phy_timing_1;		/* _DSI_PHY_TIMING_1_0 */
-	uint dsi_phy_timing_2;		/* _DSI_PHY_TIMING_2_0 */
-	uint dsi_bta_timing;		/* _DSI_BTA_TIMING_0 */
-};
-
-/* DSI timeout register 0x044 ~ 0x046 */
-struct dsi_timeout_reg {
-	/* Address 0x044 ~ 0x046 */
-	uint dsi_timeout_0;		/* _DSI_TIMEOUT_0_0 */
-	uint dsi_timeout_1;		/* _DSI_TIMEOUT_1_0 */
-	uint dsi_to_tally;		/* _DSI_TO_TALLY_0 */
-};
-
-/* DSI PAD control register 0x04b ~ 0x04e */
-struct dsi_pad_ctrl_reg {
-	/* Address 0x04b ~ 0x04e */
-	uint pad_ctrl;			/* _PAD_CONTROL_0 */
-	uint pad_ctrl_cd;		/* _PAD_CONTROL_CD_0 */
-	uint pad_cd_status;		/* _PAD_CD_STATUS_0 */
-	uint dsi_vid_mode_control;	/* _DSI_VID_MODE_CONTROL_0 */
-};
-
-/* Display Serial Interface (DSI_) regs */
-struct dsi_ctlr {
-	struct dsi_syncpt_reg syncpt;	/* SYNCPT register 0x000 ~ 0x002 */
-	uint reserved0[5];		/* reserved_0[5] */
-
-	struct dsi_misc_reg misc;	/* MISC register 0x008 ~ 0x015 */
-	uint reserved1[4];		/* reserved_1[4] */
-
-	struct dsi_init_seq_reg init;	/* INIT register 0x01a ~ 0x022 */
-	struct dsi_pkt_seq_reg pkt;	/* PKT register 0x023 ~ 0x02e */
-	uint reserved2[4];		/* reserved_2[4] */
-
-	struct dsi_pkt_len_reg len;	/* LEN registers 0x033 ~ 0x037 */
-	uint reserved3[4];		/* reserved_3[4] */
-
-	struct dsi_timing_reg ptiming;	/* TIMING registers 0x03c ~ 0x03f */
-	uint reserved4[4];		/* reserved_4[4] */
-
-	struct dsi_timeout_reg timeout;	/* TIMEOUT registers 0x044 ~ 0x046 */
-	uint reserved5[4];		/* reserved_5[4] */
-
-	struct dsi_pad_ctrl_reg pad;	/* PAD registers 0x04b ~ 0x04e */
-};
-
-#define DSI_POWER_CONTROL_ENABLE	BIT(0)
-
-#define DSI_HOST_CONTROL_FIFO_RESET	BIT(21)
-#define DSI_HOST_CONTROL_CRC_RESET	BIT(20)
-#define DSI_HOST_CONTROL_TX_TRIG_SOL	(0 << 12)
-#define DSI_HOST_CONTROL_TX_TRIG_FIFO	(1 << 12)
-#define DSI_HOST_CONTROL_TX_TRIG_HOST	(2 << 12)
-#define DSI_HOST_CONTROL_RAW		BIT(6)
-#define DSI_HOST_CONTROL_HS		BIT(5)
-#define DSI_HOST_CONTROL_FIFO_SEL	BIT(4)
-#define DSI_HOST_CONTROL_IMM_BTA	BIT(3)
-#define DSI_HOST_CONTROL_PKT_BTA	BIT(2)
-#define DSI_HOST_CONTROL_CS		BIT(1)
-#define DSI_HOST_CONTROL_ECC		BIT(0)
-
-#define DSI_CONTROL_HS_CLK_CTRL		BIT(20)
-#define DSI_CONTROL_CHANNEL(c)		(((c) & 0x3) << 16)
-#define DSI_CONTROL_FORMAT(f)		(((f) & 0x3) << 12)
-#define DSI_CONTROL_TX_TRIG(x)		(((x) & 0x3) <<  8)
-#define DSI_CONTROL_LANES(n)		(((n) & 0x3) <<  4)
-#define DSI_CONTROL_DCS_ENABLE		BIT(3)
-#define DSI_CONTROL_SOURCE(s)		(((s) & 0x1) <<  2)
-#define DSI_CONTROL_VIDEO_ENABLE	BIT(1)
-#define DSI_CONTROL_HOST_ENABLE		BIT(0)
-
-#define DSI_TRIGGER_HOST		BIT(1)
-#define DSI_TRIGGER_VIDEO		BIT(0)
-
-#define DSI_STATUS_IDLE			BIT(10)
-#define DSI_STATUS_UNDERFLOW		BIT(9)
-#define DSI_STATUS_OVERFLOW		BIT(8)
-
-#define DSI_TIMING_FIELD(value, period, hwinc) \
-	((DIV_ROUND_CLOSEST(value, period) - (hwinc)) & 0xff)
-
-#define DSI_TIMEOUT_LRX(x)		(((x) & 0xffff) << 16)
-#define DSI_TIMEOUT_HTX(x)		(((x) & 0xffff) <<  0)
-#define DSI_TIMEOUT_PR(x)		(((x) & 0xffff) << 16)
-#define DSI_TIMEOUT_TA(x)		(((x) & 0xffff) <<  0)
-
-#define DSI_TALLY_TA(x)			(((x) & 0xff) << 16)
-#define DSI_TALLY_LRX(x)		(((x) & 0xff) <<  8)
-#define DSI_TALLY_HTX(x)		(((x) & 0xff) <<  0)
-
-#define DSI_PAD_CONTROL_PAD_PULLDN_ENAB(x)	(((x) & 0x1) << 28)
-#define DSI_PAD_CONTROL_PAD_SLEWUPADJ(x)	(((x) & 0x7) << 24)
-#define DSI_PAD_CONTROL_PAD_SLEWDNADJ(x)	(((x) & 0x7) << 20)
-#define DSI_PAD_CONTROL_PAD_PREEMP_EN(x)	(((x) & 0x1) << 19)
-#define DSI_PAD_CONTROL_PAD_PDIO_CLK(x)		(((x) & 0x1) << 18)
-#define DSI_PAD_CONTROL_PAD_PDIO(x)		(((x) & 0x3) << 16)
-#define DSI_PAD_CONTROL_PAD_LPUPADJ(x)		(((x) & 0x3) << 14)
-#define DSI_PAD_CONTROL_PAD_LPDNADJ(x)		(((x) & 0x3) << 12)
-
-/*
- * pixel format as used in the DSI_CONTROL_FORMAT field
- */
-enum tegra_dsi_format {
-	TEGRA_DSI_FORMAT_16P,
-	TEGRA_DSI_FORMAT_18NP,
-	TEGRA_DSI_FORMAT_18P,
-	TEGRA_DSI_FORMAT_24P,
-};
-
-/* DSI calibration in VI region */
-#define TEGRA_VI_BASE			0x54080000
-
-#define CSI_CILA_MIPI_CAL_CONFIG_0	0x22a
-#define  MIPI_CAL_TERMOSA(x)		(((x) & 0x1f) << 0)
-
-#define CSI_CILB_MIPI_CAL_CONFIG_0	0x22b
-#define  MIPI_CAL_TERMOSB(x)		(((x) & 0x1f) << 0)
-
-#define CSI_CIL_PAD_CONFIG		0x229
-#define  PAD_CIL_PDVREG(x)		(((x) & 0x01) << 1)
-
-#define CSI_DSI_MIPI_CAL_CONFIG		0x234
-#define  MIPI_CAL_HSPDOSD(x)		(((x) & 0x1f) << 16)
-#define  MIPI_CAL_HSPUOSD(x)		(((x) & 0x1f) << 8)
-
-#define CSI_MIPIBIAS_PAD_CONFIG		0x235
-#define  PAD_DRIV_DN_REF(x)		(((x) & 0x7) << 16)
-#define  PAD_DRIV_UP_REF(x)		(((x) & 0x7) << 8)
-
-#endif /* __ASM_ARCH_TEGRA_DSI_H */
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index f68a0a48949..4f22d9bde9f 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -180,6 +180,7 @@ config ROCKCHIP_RK3328
 	select SUPPORT_TPL
 	select TPL
 	select TPL_NEEDS_SEPARATE_STACK if TPL
+	imply PRE_CONSOLE_BUFFER
 	imply ROCKCHIP_COMMON_BOARD
 	imply ROCKCHIP_SDRAM_COMMON
 	imply SPL_ROCKCHIP_COMMON_BOARD