diff options
| author | Masahiro Yamada | 2019-07-10 20:07:46 +0900 |
|---|---|---|
| committer | Masahiro Yamada | 2019-07-10 22:42:06 +0900 |
| commit | 1f8357c3ab27685fa32693ed9cba793932407a69 (patch) | |
| tree | a94fd78de8040f9ba9734b84b62576a1f9368bf4 /arch | |
| parent | 34e29f7d94aa0243793081751ea0eeae598a0273 (diff) | |
ARM: uniphier: remove CONFIG_SYS_SDRAM_BASE
The base address of DRAM was 0x80000000 for all the ARM SoCs of this
family in the past. It will be changed to 0x20000000 for a planned new
SoC. To support multiple SoCs by the single uniphier_v8_defconfig, the
base must be run-time determined.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-uniphier/dram_init.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 970fa09ef03..13821a92883 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -33,7 +33,7 @@ static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map, val = readl(sg_base + SG_MEMCONF); /* set up ch0 */ - dram_map[0].base = CONFIG_SYS_SDRAM_BASE; + dram_map[0].base = 0x80000000; switch (val & SG_MEMCONF_CH0_SZ_MASK) { case SG_MEMCONF_CH0_SZ_64M: @@ -255,6 +255,9 @@ int dram_init(void) gd->ram_size += dram_map[i].size; + if (!valid_bank_found) + gd->ram_base = dram_map[i].base; + prev_top = dram_map[i].base + dram_map[i].size; valid_bank_found = true; } |