diff options
| author | Qianyu Gong | 2016-03-23 19:11:36 +0800 |
|---|---|---|
| committer | York Sun | 2016-03-29 08:46:24 -0700 |
| commit | 2ef846e45cf0dbb9fb7d183266e4d57446592177 (patch) | |
| tree | 58cac958dea47ff0788f2f3e5fea41a1fca9bbdf /arch | |
| parent | d91721d4ac90f45fbfbbf06d0fbb8b671a964693 (diff) | |
armv8/ls1043aqds: dts: Set SPI mode for DSPI
Clock phase and polarity for DSPI flash need to be set.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/fsl-ls1043a-qds.dtsi | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi index 66efe673d93..2e9f1f917c5 100644 --- a/arch/arm/dts/fsl-ls1043a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi @@ -28,8 +28,10 @@ #address-cells = <1>; #size-cells = <1>; compatible = "spi-flash"; - reg = <0>; spi-max-frequency = <1000000>; /* input clock */ + spi-cpol; + spi-cpha; + reg = <0>; }; dflash1: sst25wf040b { @@ -37,6 +39,8 @@ #size-cells = <1>; compatible = "spi-flash"; spi-max-frequency = <3500000>; + spi-cpol; + spi-cpha; reg = <1>; }; @@ -45,6 +49,8 @@ #size-cells = <1>; compatible = "spi-flash"; spi-max-frequency = <3500000>; + spi-cpol; + spi-cpha; reg = <2>; }; }; |