diff options
| author | Biwen Li | 2019-09-25 17:48:11 +0800 |
|---|---|---|
| committer | Priyanka Jain | 2019-10-21 15:34:17 +0530 |
| commit | 3f4bc67548595258764b6fb15717b17a05b6be58 (patch) | |
| tree | eda8c737ab01abc19374c9ae2e7ba7344adfd5dd /arch | |
| parent | 3d23b6c5836c004c5f9a8281b03a2da98f20d9ff (diff) | |
armv7: ls102xa: Correct endianness of SCFG_SPARECR8 read
The patch corrects endianness of register SCFG_SPARECR8 read
in_le32 -> in_be32
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index bb169aaaf4b..00b6ad48ceb 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -72,7 +72,7 @@ static void __secure ls1_deepsleep_irq_cfg(void) * returns zero, so its value is saved to a scrachpad register to be * read, that is why we don't read it from register ippdexpcr1 itself. */ - ippdexpcr1 = in_le32(&scfg->sparecr[7]); + ippdexpcr1 = in_be32(&scfg->sparecr[7]); out_be32(&rcpm->ippdexpcr1, ippdexpcr1); if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC) |