diff options
| author | Heinrich Schuchardt | 2023-07-21 18:01:18 +0200 |
|---|---|---|
| committer | Leo Yu-Chi Liang | 2023-07-24 13:22:24 +0800 |
| commit | 6aabe229f8440c4960b904baf3aa33f692eea9a1 (patch) | |
| tree | 5a7314ebcc2d425d78126de4cd7eed11d716b5ce /arch | |
| parent | 90704967947817eecf6170daa3cea723e3110f8a (diff) | |
riscv: define a cache line size for the generic CPU
The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set.
Define the cache line size for QEMU on RISC-V to be 64 bytes.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/cpu/generic/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig index 897765c3c68..2baba229923 100644 --- a/arch/riscv/cpu/generic/Kconfig +++ b/arch/riscv/cpu/generic/Kconfig @@ -6,6 +6,7 @@ config GENERIC_RISCV bool select BINMAN if SPL select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) |