diff options
| author | Tom Rini | 2023-01-10 11:19:45 -0500 |
|---|---|---|
| committer | Tom Rini | 2023-01-20 12:27:24 -0500 |
| commit | 6e7df1d151a7a127caf3b62ff6dfc003fc2aefcd (patch) | |
| tree | ae38e9dcf468b2e4e58293561fae87895d9b549f /arch | |
| parent | ad242344681f6a0076a6bf100aa83ac9ecbea355 (diff) | |
global: Finish CONFIG -> CFG migration
At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks. Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
41 files changed, 657 insertions, 657 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 5c45c2a5ed5..b0e86785337 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -91,8 +91,8 @@ static struct cpu_type cpu_type_list[] = { #define EARLY_PGTABLE_SIZE 0x5000 static struct mm_region early_map[] = { #ifdef CONFIG_FSL_LSCH3 - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, + { CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE, + CFG_SYS_FSL_CCSR_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -101,26 +101,26 @@ static struct mm_region early_map[] = { PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE }, { CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1, - CONFIG_SYS_FSL_QSPI_SIZE1, + CFG_SYS_FSL_QSPI_SIZE1, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, #ifdef CONFIG_FSL_IFC /* For IFC Region #1, only the first 4MB is cache-enabled */ - { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, - CONFIG_SYS_FSL_IFC_SIZE1_1, + { CFG_SYS_FSL_IFC_BASE1, CFG_SYS_FSL_IFC_BASE1, + CFG_SYS_FSL_IFC_SIZE1_1, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE }, - { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, - CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, - CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, + { CFG_SYS_FSL_IFC_BASE1 + CFG_SYS_FSL_IFC_SIZE1_1, + CFG_SYS_FSL_IFC_BASE1 + CFG_SYS_FSL_IFC_SIZE1_1, + CFG_SYS_FSL_IFC_SIZE1 - CFG_SYS_FSL_IFC_SIZE1_1, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, - { CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, - CONFIG_SYS_FSL_IFC_SIZE1, + { CFG_SYS_FLASH_BASE, CFG_SYS_FSL_IFC_BASE1, + CFG_SYS_FSL_IFC_SIZE1, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, #endif - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, + { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1, + CFG_SYS_FSL_DRAM_SIZE1, #if defined(CONFIG_TFABOOT) || \ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) PTE_BLOCK_MEMTYPE(MT_NORMAL) | @@ -131,31 +131,31 @@ static struct mm_region early_map[] = { }, #ifdef CONFIG_FSL_IFC /* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */ - { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, - CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, + { CFG_SYS_FSL_IFC_BASE2, CFG_SYS_FSL_IFC_BASE2, + CFG_SYS_FLASH_BASE - CFG_SYS_FSL_IFC_BASE2, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, #endif - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, + { CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE, + CFG_SYS_FSL_DCSR_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, + { CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2, + CFG_SYS_FSL_DRAM_SIZE2, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, -#ifdef CONFIG_SYS_FSL_DRAM_BASE3 - { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, - CONFIG_SYS_FSL_DRAM_SIZE3, +#ifdef CFG_SYS_FSL_DRAM_BASE3 + { CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3, + CFG_SYS_FSL_DRAM_SIZE3, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #endif #elif defined(CONFIG_FSL_LSCH2) - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, + { CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE, + CFG_SYS_FSL_CCSR_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -163,23 +163,23 @@ static struct mm_region early_map[] = { SYS_FSL_OCRAM_SPACE_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE }, - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, + { CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE, + CFG_SYS_FSL_DCSR_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE, - CONFIG_SYS_FSL_QSPI_SIZE, + CFG_SYS_FSL_QSPI_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, #ifdef CONFIG_FSL_IFC - { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, - CONFIG_SYS_FSL_IFC_SIZE, + { CFG_SYS_FSL_IFC_BASE, CFG_SYS_FSL_IFC_BASE, + CFG_SYS_FSL_IFC_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, #endif - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, + { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1, + CFG_SYS_FSL_DRAM_SIZE1, #if defined(CONFIG_TFABOOT) || \ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) PTE_BLOCK_MEMTYPE(MT_NORMAL) | @@ -188,8 +188,8 @@ static struct mm_region early_map[] = { #endif PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, + { CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2, + CFG_SYS_FSL_DRAM_SIZE2, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, @@ -199,8 +199,8 @@ static struct mm_region early_map[] = { static struct mm_region final_map[] = { #ifdef CONFIG_FSL_LSCH3 - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, + { CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE, + CFG_SYS_FSL_CCSR_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -208,52 +208,52 @@ static struct mm_region final_map[] = { SYS_FSL_OCRAM_SPACE_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE }, - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, + { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1, + CFG_SYS_FSL_DRAM_SIZE1, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, { CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1, - CONFIG_SYS_FSL_QSPI_SIZE1, + CFG_SYS_FSL_QSPI_SIZE1, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { CFG_SYS_FSL_QSPI_BASE2, CFG_SYS_FSL_QSPI_BASE2, - CONFIG_SYS_FSL_QSPI_SIZE2, + CFG_SYS_FSL_QSPI_SIZE2, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, #ifdef CONFIG_FSL_IFC - { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, - CONFIG_SYS_FSL_IFC_SIZE2, + { CFG_SYS_FSL_IFC_BASE2, CFG_SYS_FSL_IFC_BASE2, + CFG_SYS_FSL_IFC_SIZE2, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, #endif - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, + { CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE, + CFG_SYS_FSL_DCSR_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, - CONFIG_SYS_FSL_MC_SIZE, + { CFG_SYS_FSL_MC_BASE, CFG_SYS_FSL_MC_BASE, + CFG_SYS_FSL_MC_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, - CONFIG_SYS_FSL_NI_SIZE, + { CFG_SYS_FSL_NI_BASE, CFG_SYS_FSL_NI_BASE, + CFG_SYS_FSL_NI_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, /* For QBMAN portal, only the first 64MB is cache-enabled */ - { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE_1, + { CFG_SYS_FSL_QBMAN_BASE, CFG_SYS_FSL_QBMAN_BASE, + CFG_SYS_FSL_QBMAN_SIZE_1, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS }, - { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, - CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, - CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, + { CFG_SYS_FSL_QBMAN_BASE + CFG_SYS_FSL_QBMAN_SIZE_1, + CFG_SYS_FSL_QBMAN_BASE + CFG_SYS_FSL_QBMAN_SIZE_1, + CFG_SYS_FSL_QBMAN_SIZE - CFG_SYS_FSL_QBMAN_SIZE_1, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -295,29 +295,29 @@ static struct mm_region final_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, #endif - { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, - CONFIG_SYS_FSL_WRIOP1_SIZE, + { CFG_SYS_FSL_WRIOP1_BASE, CFG_SYS_FSL_WRIOP1_BASE, + CFG_SYS_FSL_WRIOP1_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, - CONFIG_SYS_FSL_AIOP1_SIZE, + { CFG_SYS_FSL_AIOP1_BASE, CFG_SYS_FSL_AIOP1_BASE, + CFG_SYS_FSL_AIOP1_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, - CONFIG_SYS_FSL_PEBUF_SIZE, + { CFG_SYS_FSL_PEBUF_BASE, CFG_SYS_FSL_PEBUF_BASE, + CFG_SYS_FSL_PEBUF_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, + { CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2, + CFG_SYS_FSL_DRAM_SIZE2, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, -#ifdef CONFIG_SYS_FSL_DRAM_BASE3 - { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, - CONFIG_SYS_FSL_DRAM_SIZE3, +#ifdef CFG_SYS_FSL_DRAM_BASE3 + { CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3, + CFG_SYS_FSL_DRAM_SIZE3, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, @@ -328,8 +328,8 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, + { CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE, + CFG_SYS_FSL_CCSR_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -337,34 +337,34 @@ static struct mm_region final_map[] = { SYS_FSL_OCRAM_SPACE_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE }, - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, + { CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE, + CFG_SYS_FSL_DCSR_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE, - CONFIG_SYS_FSL_QSPI_SIZE, + CFG_SYS_FSL_QSPI_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, #ifdef CONFIG_FSL_IFC - { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, - CONFIG_SYS_FSL_IFC_SIZE, + { CFG_SYS_FSL_IFC_BASE, CFG_SYS_FSL_IFC_BASE, + CFG_SYS_FSL_IFC_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, #endif - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, + { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1, + CFG_SYS_FSL_DRAM_SIZE1, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, - { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE, + { CFG_SYS_FSL_QBMAN_BASE, CFG_SYS_FSL_QBMAN_BASE, + CFG_SYS_FSL_QBMAN_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, + { CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2, + CFG_SYS_FSL_DRAM_SIZE2, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, @@ -385,8 +385,8 @@ static struct mm_region final_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, #endif - { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, - CONFIG_SYS_FSL_DRAM_SIZE3, + { CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3, + CFG_SYS_FSL_DRAM_SIZE3, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, @@ -536,13 +536,13 @@ static inline void final_mmu_setup(void) * table. */ switch (final_map[index].virt) { - case CONFIG_SYS_FSL_DRAM_BASE1: + case CFG_SYS_FSL_DRAM_BASE1: final_map[index].virt = gd->bd->bi_dram[0].start; final_map[index].phys = gd->bd->bi_dram[0].start; final_map[index].size = gd->bd->bi_dram[0].size; break; -#ifdef CONFIG_SYS_FSL_DRAM_BASE2 - case CONFIG_SYS_FSL_DRAM_BASE2: +#ifdef CFG_SYS_FSL_DRAM_BASE2 + case CFG_SYS_FSL_DRAM_BASE2: #if (CONFIG_NR_DRAM_BANKS >= 2) final_map[index].virt = gd->bd->bi_dram[1].start; final_map[index].phys = gd->bd->bi_dram[1].start; @@ -552,8 +552,8 @@ static inline void final_mmu_setup(void) #endif break; #endif -#ifdef CONFIG_SYS_FSL_DRAM_BASE3 - case CONFIG_SYS_FSL_DRAM_BASE3: +#ifdef CFG_SYS_FSL_DRAM_BASE3 + case CFG_SYS_FSL_DRAM_BASE3: #if (CONFIG_NR_DRAM_BANKS >= 3) final_map[index].virt = gd->bd->bi_dram[2].start; final_map[index].phys = gd->bd->bi_dram[2].start; @@ -1566,7 +1566,7 @@ void update_early_mmu_table(void) if (!gd->arch.tlb_addr) return; - if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) { + if (gd->ram_size <= CFG_SYS_FSL_DRAM_SIZE1) { mmu_change_region_attr( CFG_SYS_SDRAM_BASE, gd->ram_size, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 20f96713871..444b56606a7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -8,32 +8,32 @@ #define _FSL_LAYERSCAPE_CPU_H #ifdef CONFIG_FSL_LSCH3 -#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 -#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 +#define CFG_SYS_FSL_CCSR_BASE 0x00000000 +#define CFG_SYS_FSL_CCSR_SIZE 0x10000000 #define CFG_SYS_FSL_QSPI_BASE1 0x20000000 -#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 +#define CFG_SYS_FSL_QSPI_SIZE1 0x10000000 #ifndef CONFIG_NXP_LSCH3_2 -#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 -#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 -#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 +#define CFG_SYS_FSL_IFC_BASE1 0x30000000 +#define CFG_SYS_FSL_IFC_SIZE1 0x10000000 +#define CFG_SYS_FSL_IFC_SIZE1_1 0x400000 #endif -#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 -#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 +#define CFG_SYS_FSL_DRAM_BASE1 0x80000000 +#define CFG_SYS_FSL_DRAM_SIZE1 0x80000000 #define CFG_SYS_FSL_QSPI_BASE2 0x400000000 -#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 +#define CFG_SYS_FSL_QSPI_SIZE2 0x100000000 #ifndef CONFIG_NXP_LSCH3_2 -#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 -#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 +#define CFG_SYS_FSL_IFC_BASE2 0x500000000 +#define CFG_SYS_FSL_IFC_SIZE2 0x100000000 #endif -#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 -#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 -#define CONFIG_SYS_FSL_MC_BASE 0x80c000000 -#define CONFIG_SYS_FSL_MC_SIZE 0x4000000 -#define CONFIG_SYS_FSL_NI_BASE 0x810000000 -#define CONFIG_SYS_FSL_NI_SIZE 0x8000000 -#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 -#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 -#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 +#define CFG_SYS_FSL_DCSR_BASE 0x700000000 +#define CFG_SYS_FSL_DCSR_SIZE 0x40000000 +#define CFG_SYS_FSL_MC_BASE 0x80c000000 +#define CFG_SYS_FSL_MC_SIZE 0x4000000 +#define CFG_SYS_FSL_NI_BASE 0x810000000 +#define CFG_SYS_FSL_NI_SIZE 0x8000000 +#define CFG_SYS_FSL_QBMAN_BASE 0x818000000 +#define CFG_SYS_FSL_QBMAN_SIZE 0x8000000 +#define CFG_SYS_FSL_QBMAN_SIZE_1 0x4000000 #ifdef CONFIG_ARCH_LS2080A #define CFG_SYS_PCIE1_PHYS_SIZE 0x200000000 #define CFG_SYS_PCIE2_PHYS_SIZE 0x200000000 @@ -49,45 +49,45 @@ #define SYS_PCIE5_PHYS_SIZE 0x800000000 #define SYS_PCIE6_PHYS_SIZE 0x800000000 #endif -#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 -#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 -#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 -#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 +#define CFG_SYS_FSL_WRIOP1_BASE 0x4300000000 +#define CFG_SYS_FSL_WRIOP1_SIZE 0x100000000 +#define CFG_SYS_FSL_AIOP1_BASE 0x4b00000000 +#define CFG_SYS_FSL_AIOP1_SIZE 0x100000000 #if !defined(CONFIG_ARCH_LX2160A) || !defined(CONFIG_ARCH_LX2162) -#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 +#define CFG_SYS_FSL_PEBUF_BASE 0x4c00000000 #else -#define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000 +#define CFG_SYS_FSL_PEBUF_BASE 0x1c00000000 #endif -#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 +#define CFG_SYS_FSL_PEBUF_SIZE 0x400000000 #ifdef CONFIG_NXP_LSCH3_2 -#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000 -#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000 -#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000 -#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000 +#define CFG_SYS_FSL_DRAM_BASE2 0x2080000000 +#define CFG_SYS_FSL_DRAM_SIZE2 0x1F80000000 +#define CFG_SYS_FSL_DRAM_BASE3 0x6000000000 +#define CFG_SYS_FSL_DRAM_SIZE3 0x2000000000 #else -#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 -#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 +#define CFG_SYS_FSL_DRAM_BASE2 0x8080000000 +#define CFG_SYS_FSL_DRAM_SIZE2 0x7F80000000 #endif #elif defined(CONFIG_FSL_LSCH2) -#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000 -#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000 -#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000 -#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000 +#define CFG_SYS_FSL_CCSR_BASE 0x1000000 +#define CFG_SYS_FSL_CCSR_SIZE 0xf000000 +#define CFG_SYS_FSL_DCSR_BASE 0x20000000 +#define CFG_SYS_FSL_DCSR_SIZE 0x4000000 #define CFG_SYS_FSL_QSPI_BASE 0x40000000 -#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000 -#define CONFIG_SYS_FSL_IFC_BASE 0x60000000 -#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000 -#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 -#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 -#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000 -#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 -#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 -#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ +#define CFG_SYS_FSL_QSPI_SIZE 0x20000000 +#define CFG_SYS_FSL_IFC_BASE 0x60000000 +#define CFG_SYS_FSL_IFC_SIZE 0x20000000 +#define CFG_SYS_FSL_DRAM_BASE1 0x80000000 +#define CFG_SYS_FSL_DRAM_SIZE1 0x80000000 +#define CFG_SYS_FSL_QBMAN_BASE 0x500000000 +#define CFG_SYS_FSL_QBMAN_SIZE 0x10000000 +#define CFG_SYS_FSL_DRAM_BASE2 0x880000000 +#define CFG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ #define CFG_SYS_PCIE1_PHYS_SIZE 0x800000000 #define CFG_SYS_PCIE2_PHYS_SIZE 0x800000000 #define CFG_SYS_PCIE3_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 -#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ +#define CFG_SYS_FSL_DRAM_BASE3 0x8800000000 +#define CFG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ #endif int fsl_qoriq_core_to_cluster(unsigned int core); diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h index 979d5470e7a..43ccae10bdf 100644 --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h @@ -360,7 +360,7 @@ check_member(rk3288_msch, devtodev, 0x003c); #define PCTL_STAT_MSK 7 #define INIT_MEM 0 #define CONFIG 1 -#define CONFIG_REQ 2 +#define CFG_REQ 2 #define ACCESS 3 #define ACCESS_REQ 4 #define LOW_POWER 5 diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h index 6f6c5c9954f..0d29aefb646 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h @@ -415,7 +415,7 @@ struct rk322x_base_params { #define PCTL_STAT_MASK 7 #define INIT_MEM 0 #define CONFIG 1 -#define CONFIG_REQ 2 +#define CFG_REQ 2 #define ACCESS 3 #define ACCESS_REQ 4 #define LOW_POWER 5 diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index e3dcfdf3708..f0da46d863c 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -14,7 +14,7 @@ #define CFG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE #endif #ifdef CONFIG_R_I2C_ENABLE -#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE +#define CFG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE #endif /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ diff --git a/arch/arm/mach-omap2/fdt-common.c b/arch/arm/mach-omap2/fdt-common.c index 5eb04473123..e90d5776703 100644 --- a/arch/arm/mach-omap2/fdt-common.c +++ b/arch/arm/mach-omap2/fdt-common.c @@ -17,8 +17,8 @@ #ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0) #endif -#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ -#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0) +#ifndef CFG_SECURE_RUNTIME_RESV_SRAM_SZ +#define CFG_SECURE_RUNTIME_RESV_SRAM_SZ (0) #endif int ft_hs_disable_rng(void *fdt, struct bd_info *bd) diff --git a/arch/arm/mach-omap2/omap5/fdt.c b/arch/arm/mach-omap2/omap5/fdt.c index c4162420f3a..a8c301c6c28 100644 --- a/arch/arm/mach-omap2/omap5/fdt.c +++ b/arch/arm/mach-omap2/omap5/fdt.c @@ -19,8 +19,8 @@ #ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0) #endif -#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ -#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0) +#ifndef CFG_SECURE_RUNTIME_RESV_SRAM_SZ +#define CFG_SECURE_RUNTIME_RESV_SRAM_SZ (0) #endif static u32 hs_irq_skip[] = { @@ -92,7 +92,7 @@ static int ft_hs_fixup_crossbar(void *fdt, struct bd_info *bd) } #if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \ - (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0)) + (CFG_SECURE_RUNTIME_RESV_SRAM_SZ != 0)) static int ft_hs_fixup_sram(void *fdt, struct bd_info *bd) { const char *path; @@ -116,7 +116,7 @@ static int ft_hs_fixup_sram(void *fdt, struct bd_info *bd) temp[0] = cpu_to_fdt32(0); /* reservation size */ temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ, - CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ)); + CFG_SECURE_RUNTIME_RESV_SRAM_SZ)); fdt_delprop(fdt, offs, "reg"); ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32)); if (ret < 0) { diff --git a/arch/arm/mach-rmobile/include/mach/rcar-mstp.h b/arch/arm/mach-rmobile/include/mach/rcar-mstp.h index f2f8ce95992..d241652641f 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-mstp.h +++ b/arch/arm/mach-rmobile/include/mach/rcar-mstp.h @@ -22,78 +22,78 @@ #define mstp_setclrbits_le32(addr, set, clear) \ mstp_setclrbits(le32, addr, set, clear) -#ifndef CONFIG_SMSTP0_ENA -#define CONFIG_SMSTP0_ENA 0x00 +#ifndef CFG_SMSTP0_ENA +#define CFG_SMSTP0_ENA 0x00 #endif -#ifndef CONFIG_SMSTP1_ENA -#define CONFIG_SMSTP1_ENA 0x00 +#ifndef CFG_SMSTP1_ENA +#define CFG_SMSTP1_ENA 0x00 #endif -#ifndef CONFIG_SMSTP2_ENA -#define CONFIG_SMSTP2_ENA 0x00 +#ifndef CFG_SMSTP2_ENA +#define CFG_SMSTP2_ENA 0x00 #endif -#ifndef CONFIG_SMSTP3_ENA -#define CONFIG_SMSTP3_ENA 0x00 +#ifndef CFG_SMSTP3_ENA +#define CFG_SMSTP3_ENA 0x00 #endif -#ifndef CONFIG_SMSTP4_ENA -#define CONFIG_SMSTP4_ENA 0x00 +#ifndef CFG_SMSTP4_ENA +#define CFG_SMSTP4_ENA 0x00 #endif -#ifndef CONFIG_SMSTP5_ENA -#define CONFIG_SMSTP5_ENA 0x00 +#ifndef CFG_SMSTP5_ENA +#define CFG_SMSTP5_ENA 0x00 #endif -#ifndef CONFIG_SMSTP6_ENA -#define CONFIG_SMSTP6_ENA 0x00 +#ifndef CFG_SMSTP6_ENA +#define CFG_SMSTP6_ENA 0x00 #endif -#ifndef CONFIG_SMSTP7_ENA -#define CONFIG_SMSTP7_ENA 0x00 +#ifndef CFG_SMSTP7_ENA +#define CFG_SMSTP7_ENA 0x00 #endif -#ifndef CONFIG_SMSTP8_ENA -#define CONFIG_SMSTP8_ENA 0x00 +#ifndef CFG_SMSTP8_ENA +#define CFG_SMSTP8_ENA 0x00 #endif -#ifndef CONFIG_SMSTP9_ENA -#define CONFIG_SMSTP9_ENA 0x00 +#ifndef CFG_SMSTP9_ENA +#define CFG_SMSTP9_ENA 0x00 #endif -#ifndef CONFIG_SMSTP10_ENA -#define CONFIG_SMSTP10_ENA 0x00 +#ifndef CFG_SMSTP10_ENA +#define CFG_SMSTP10_ENA 0x00 #endif -#ifndef CONFIG_SMSTP11_ENA -#define CONFIG_SMSTP11_ENA 0x00 +#ifndef CFG_SMSTP11_ENA +#define CFG_SMSTP11_ENA 0x00 #endif -#ifndef CONFIG_RMSTP0_ENA -#define CONFIG_RMSTP0_ENA 0x00 +#ifndef CFG_RMSTP0_ENA +#define CFG_RMSTP0_ENA 0x00 #endif -#ifndef CONFIG_RMSTP1_ENA -#define CONFIG_RMSTP1_ENA 0x00 +#ifndef CFG_RMSTP1_ENA +#define CFG_RMSTP1_ENA 0x00 #endif -#ifndef CONFIG_RMSTP2_ENA -#define CONFIG_RMSTP2_ENA 0x00 +#ifndef CFG_RMSTP2_ENA +#define CFG_RMSTP2_ENA 0x00 #endif -#ifndef CONFIG_RMSTP3_ENA -#define CONFIG_RMSTP3_ENA 0x00 +#ifndef CFG_RMSTP3_ENA +#define CFG_RMSTP3_ENA 0x00 #endif -#ifndef CONFIG_RMSTP4_ENA -#define CONFIG_RMSTP4_ENA 0x00 +#ifndef CFG_RMSTP4_ENA +#define CFG_RMSTP4_ENA 0x00 #endif -#ifndef CONFIG_RMSTP5_ENA -#define CONFIG_RMSTP5_ENA 0x00 +#ifndef CFG_RMSTP5_ENA +#define CFG_RMSTP5_ENA 0x00 #endif -#ifndef CONFIG_RMSTP6_ENA -#define CONFIG_RMSTP6_ENA 0x00 +#ifndef CFG_RMSTP6_ENA +#define CFG_RMSTP6_ENA 0x00 #endif -#ifndef CONFIG_RMSTP7_ENA -#define CONFIG_RMSTP7_ENA 0x00 +#ifndef CFG_RMSTP7_ENA +#define CFG_RMSTP7_ENA 0x00 #endif -#ifndef CONFIG_RMSTP8_ENA -#define CONFIG_RMSTP8_ENA 0x00 +#ifndef CFG_RMSTP8_ENA +#define CFG_RMSTP8_ENA 0x00 #endif -#ifndef CONFIG_RMSTP9_ENA -#define CONFIG_RMSTP9_ENA 0x00 +#ifndef CFG_RMSTP9_ENA +#define CFG_RMSTP9_ENA 0x00 #endif -#ifndef CONFIG_RMSTP10_ENA -#define CONFIG_RMSTP10_ENA 0x00 +#ifndef CFG_RMSTP10_ENA +#define CFG_RMSTP10_ENA 0x00 #endif -#ifndef CONFIG_RMSTP11_ENA -#define CONFIG_RMSTP11_ENA 0x00 +#ifndef CFG_RMSTP11_ENA +#define CFG_RMSTP11_ENA 0x00 #endif struct mstp_ctl { diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index 6ae254e99af..fcae65b2e5a 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -198,7 +198,7 @@ enum { /* PCTL_STAT */ INIT_MEM = 0, CONFIG, - CONFIG_REQ, + CFG_REQ, ACCESS, ACCESS_REQ, LOW_POWER, diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index be801d108e3..94ce762e01f 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -34,7 +34,7 @@ void wb_start(void) u32 reg; /* enable JTAG & TBE */ - writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl); + writel(CFG_CTL_TBE | CFG_CTL_JTAG, &apb_misc->cfg_ctl); /* Are we running where we're supposed to be? */ asm volatile ( diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.h b/arch/arm/mach-tegra/tegra20/warmboot_avp.h index 19a476b8957..f300fe66254 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.h +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.h @@ -19,8 +19,8 @@ #define USEC_CFG_DIVISOR_MASK 0xffff -#define CONFIG_CTL_TBE (1 << 7) -#define CONFIG_CTL_JTAG (1 << 6) +#define CFG_CTL_TBE (1 << 7) +#define CFG_CTL_JTAG (1 << 6) #define CPU_RST (1 << 0) #define CLK_ENB_CPU (1 << 0) diff --git a/arch/m68k/cpu/mcf523x/interrupts.c b/arch/m68k/cpu/mcf523x/interrupts.c index b554c51fcbe..331288e0060 100644 --- a/arch/m68k/cpu/mcf523x/interrupts.c +++ b/arch/m68k/cpu/mcf523x/interrupts.c @@ -13,7 +13,7 @@ int interrupt_init(void) { - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ setbits_be32(&intp->imrl0, 0x1); @@ -25,10 +25,10 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); - out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI); clrbits_be32(&intp->imrl0, INTC_IPRL_INT0); - clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK); + clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK); } #endif diff --git a/arch/m68k/cpu/mcf52x2/interrupts.c b/arch/m68k/cpu/mcf52x2/interrupts.c index 35ed1e7901b..e8a1e132d27 100644 --- a/arch/m68k/cpu/mcf52x2/interrupts.c +++ b/arch/m68k/cpu/mcf52x2/interrupts.c @@ -37,10 +37,10 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE); + intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE); clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK); - setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI); + setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI); } #endif /* CONFIG_MCFTMR */ #endif /* CONFIG_M5272 */ @@ -49,7 +49,7 @@ void dtimer_intr_setup(void) defined(CONFIG_M5271) || defined(CONFIG_M5275) int interrupt_init(void) { - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ #if defined(CONFIG_M5208) @@ -66,11 +66,11 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); - out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI); clrbits_be32(&intp->imrl0, 0x00000001); - clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK); + clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK); } #endif /* CONFIG_MCFTMR */ #endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */ @@ -87,7 +87,7 @@ int interrupt_init(void) void dtimer_intr_setup(void) { mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); - mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI); + mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI); } #endif /* CONFIG_MCFTMR */ #endif /* CONFIG_M5249 || CONFIG_M5253 */ diff --git a/arch/m68k/cpu/mcf530x/interrupts.c b/arch/m68k/cpu/mcf530x/interrupts.c index 2659e3478f0..11686202dc7 100644 --- a/arch/m68k/cpu/mcf530x/interrupts.c +++ b/arch/m68k/cpu/mcf530x/interrupts.c @@ -24,6 +24,6 @@ void dtimer_intr_setup(void) /* clearing TIMER2 mask, so enabling the related interrupt */ out_be32(&icr->imr, in_be32(&icr->imr) & ~0x00000400); /* set TIMER2 interrupt priority */ - out_8(&icr->icr2, CONFIG_SYS_TMRINTR_PRI); + out_8(&icr->icr2, CFG_SYS_TMRINTR_PRI); } #endif diff --git a/arch/m68k/cpu/mcf532x/interrupts.c b/arch/m68k/cpu/mcf532x/interrupts.c index 8f2df452bae..64e04664a52 100644 --- a/arch/m68k/cpu/mcf532x/interrupts.c +++ b/arch/m68k/cpu/mcf532x/interrupts.c @@ -13,7 +13,7 @@ int interrupt_init(void) { - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ setbits_be32(&intp->imrh0, 0xffffffff); @@ -26,9 +26,9 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); - out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); - clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); + out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrh0, CFG_SYS_TMRINTR_MASK); } #endif diff --git a/arch/m68k/cpu/mcf5445x/interrupts.c b/arch/m68k/cpu/mcf5445x/interrupts.c index 5a6a88cd571..ea0cf87990c 100644 --- a/arch/m68k/cpu/mcf5445x/interrupts.c +++ b/arch/m68k/cpu/mcf5445x/interrupts.c @@ -16,7 +16,7 @@ int interrupt_init(void) { - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ setbits_be32(&intp->imrh0, 0xffffffff); @@ -29,9 +29,9 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE); - out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); - clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); + out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrh0, CFG_SYS_TMRINTR_MASK); } #endif diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index c05356fc930..8ed2b4dbab4 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -11,21 +11,21 @@ #if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \ defined(CONFIG_MCF52x2) -#define CONFIG_CF_V2 +#define CFG_CF_V2 #endif #if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \ defined(CONFIG_MCF5301x) -#define CONFIG_CF_V3 +#define CFG_CF_V3 #endif #if defined(CONFIG_MCF5441x) -#define CONFIG_CF_V4E /* Four Extra ACRn */ +#define CFG_CF_V4E /* Four Extra ACRn */ #endif /* ***** CACR ***** */ /* V2 Core */ -#ifdef CONFIG_CF_V2 +#ifdef CFG_CF_V2 #define CF_CACR_CENB (1 << 31) #define CF_CACR_CPD (1 << 28) @@ -46,10 +46,10 @@ #define CF_CACR_EUSP (1 << 4) #endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */ -#endif /* CONFIG_CF_V2 */ +#endif /* CFG_CF_V2 */ /* V3 Core */ -#ifdef CONFIG_CF_V3 +#ifdef CFG_CF_V3 #define CF_CACR_EC (1 << 31) #define CF_CACR_ESB (1 << 29) @@ -65,10 +65,10 @@ #define CF_CACR_DW (1 << 5) #define CF_CACR_EUSP (1 << 4) -#endif /* CONFIG_CF_V3 */ +#endif /* CFG_CF_V3 */ /* V4 Core */ -#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) +#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E) #define CF_CACR_DEC (1 << 31) #define CF_CACR_DW (1 << 30) @@ -116,7 +116,7 @@ #define CF_ACR_WP (1 << 2) /* V2 Core */ -#ifdef CONFIG_CF_V2 +#ifdef CFG_CF_V2 #define CF_ACR_CM (1 << 6) #define CF_ACR_BWE (1 << 5) #else @@ -126,10 +126,10 @@ #define CF_ACR_CM_CB (1 << 5) #define CF_ACR_CM_P (2 << 5) #define CF_ACR_CM_IP (3 << 5) -#endif /* CONFIG_CF_V2 */ +#endif /* CFG_CF_V2 */ /* V4 Core */ -#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) +#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E) #define CF_ACR_AMM (1 << 10) #define CF_ACR_SP (1 << 3) #endif /* CONFIG_CF_V4 */ @@ -159,24 +159,24 @@ #define CFG_SYS_CACHE_ACR2 0 #endif -#ifndef CONFIG_SYS_CACHE_ACR3 -#define CONFIG_SYS_CACHE_ACR3 0 +#ifndef CFG_SYS_CACHE_ACR3 +#define CFG_SYS_CACHE_ACR3 0 #endif -#ifndef CONFIG_SYS_CACHE_ACR4 -#define CONFIG_SYS_CACHE_ACR4 0 +#ifndef CFG_SYS_CACHE_ACR4 +#define CFG_SYS_CACHE_ACR4 0 #endif -#ifndef CONFIG_SYS_CACHE_ACR5 -#define CONFIG_SYS_CACHE_ACR5 0 +#ifndef CFG_SYS_CACHE_ACR5 +#define CFG_SYS_CACHE_ACR5 0 #endif -#ifndef CONFIG_SYS_CACHE_ACR6 -#define CONFIG_SYS_CACHE_ACR6 0 +#ifndef CFG_SYS_CACHE_ACR6 +#define CFG_SYS_CACHE_ACR6 0 #endif -#ifndef CONFIG_SYS_CACHE_ACR7 -#define CONFIG_SYS_CACHE_ACR7 0 +#ifndef CFG_SYS_CACHE_ACR7 +#define CFG_SYS_CACHE_ACR7 0 #endif #define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16) diff --git a/arch/m68k/include/asm/coldfire/intctrl.h b/arch/m68k/include/asm/coldfire/intctrl.h index f7f0f07d30f..3f7c458ef08 100644 --- a/arch/m68k/include/asm/coldfire/intctrl.h +++ b/arch/m68k/include/asm/coldfire/intctrl.h @@ -12,7 +12,7 @@ #if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \ defined(CONFIG_M5275) || defined(CONFIG_M5282) || \ defined(CONFIG_M547x) -# define CONFIG_SYS_CF_INTC_REG1 +# define CFG_SYS_CF_INTC_REG1 #endif typedef struct int0_ctrl { @@ -23,7 +23,7 @@ typedef struct int0_ctrl { u32 imrl0; /* 0x0C Mask Low */ u32 frch0; /* 0x10 Force High */ u32 frcl0; /* 0x14 Force Low */ -#if defined(CONFIG_SYS_CF_INTC_REG1) +#if defined(CFG_SYS_CF_INTC_REG1) u8 irlr; /* 0x18 */ u8 iacklpr; /* 0x19 */ u16 res1[19]; /* 0x1a - 0x3c */ @@ -64,7 +64,7 @@ typedef struct int1_ctrl { u32 imrl1; /* 0x0C Mask Low */ u32 frch1; /* 0x10 Force High */ u32 frcl1; /* 0x14 Force Low */ -#if defined(CONFIG_SYS_CF_INTC_REG1) +#if defined(CFG_SYS_CF_INTC_REG1) u8 irlr; /* 0x18 */ u8 iacklpr; /* 0x19 */ u16 res1[19]; /* 0x1a - 0x3c */ @@ -192,7 +192,7 @@ typedef struct intgack_ctrl1 { #define INTC_IACKLPR_PRI(x) ((x) & 0x0F) #define INTC_IACKLPR_PRI_MASK (0xF0) -#if defined(CONFIG_SYS_CF_INTC_REG1) +#if defined(CFG_SYS_CF_INTC_REG1) #define INTC_ICR_IL(x) (((x) & 0x07) << 3) #define INTC_ICR_IL_MASK (0xC7) #define INTC_ICR_IP(x) ((x) & 0x07) diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index 0c23744a867..8207c8d5b73 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -13,65 +13,65 @@ #include <asm/immap_520x.h> #include <asm/m520x.h> -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) +#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) /* Timer */ #ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) -#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (6) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CFG_SYS_TMR_BASE (MMAP_DTMR1) +#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0) +#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1) +#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) +#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) +#define CFG_SYS_TMRINTR_PRI (6) +#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) +#define CFG_SYS_INTR_BASE (MMAP_INTC0) +#define CFG_SYS_NUM_IRQS (128) #endif /* CONFIG_M520x */ #ifdef CONFIG_M5235 #include <asm/immap_5235.h> #include <asm/m5235.h> -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) +#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) /* Timer */ #ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) -#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CFG_SYS_TMR_BASE (MMAP_DTMR3) +#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0) +#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3) +#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) +#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) +#define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ +#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) +#define CFG_SYS_INTR_BASE (MMAP_INTC0) +#define CFG_SYS_NUM_IRQS (128) #endif /* CONFIG_M5235 */ #ifdef CONFIG_M5249 #include <asm/immap_5249.h> #include <asm/m5249.h> -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) +#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) -#define CONFIG_SYS_INTR_BASE (MMAP_INTC) -#define CONFIG_SYS_NUM_IRQS (64) +#define CFG_SYS_INTR_BASE (MMAP_INTC) +#define CFG_SYS_NUM_IRQS (64) /* Timer */ #ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) -#define CONFIG_SYS_TMRINTR_NO (31) -#define CONFIG_SYS_TMRINTR_MASK (0x00000400) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) +#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CFG_SYS_TMR_BASE (MMAP_DTMR1) +#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) +#define CFG_SYS_TMRINTR_NO (31) +#define CFG_SYS_TMRINTR_MASK (0x00000400) +#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) +#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) +#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) #endif #endif /* CONFIG_M5249 */ @@ -80,21 +80,21 @@ #include <asm/m5249.h> #include <asm/m5253.h> -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) +#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) -#define CONFIG_SYS_INTR_BASE (MMAP_INTC) -#define CONFIG_SYS_NUM_IRQS (64) +#define CFG_SYS_INTR_BASE (MMAP_INTC) +#define CFG_SYS_NUM_IRQS (64) /* Timer */ #ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) -#define CONFIG_SYS_TMRINTR_NO (27) -#define CONFIG_SYS_TMRINTR_MASK (0x00000400) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) +#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CFG_SYS_TMR_BASE (MMAP_DTMR1) +#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) +#define CFG_SYS_TMRINTR_NO (27) +#define CFG_SYS_TMRINTR_MASK (0x00000400) +#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) +#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3) +#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) #endif #endif /* CONFIG_M5253 */ @@ -102,43 +102,43 @@ #include <asm/immap_5271.h> #include <asm/m5271.h> -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) +#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) /* Timer */ #ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) -#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */ -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CFG_SYS_TMR_BASE (MMAP_DTMR3) +#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0) +#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3) +#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) +#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) +#define CFG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */ +#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) +#define CFG_SYS_INTR_BASE (MMAP_INTC0) +#define CFG_SYS_NUM_IRQS (128) #endif /* CONFIG_M5271 */ #ifdef CONFIG_M5272 #include <asm/immap_5272.h> #include <asm/m5272.h> -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) +#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) -#define CONFIG_SYS_INTR_BASE (MMAP_INTC) -#define CONFIG_SYS_NUM_IRQS (64) +#define CFG_SYS_INTR_BASE (MMAP_INTC) +#define CFG_SYS_NUM_IRQS (64) /* Timer */ #ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_TMR3) -#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr) -#define CONFIG_SYS_TMRINTR_NO (INT_TMR3) -#define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24) -#define CONFIG_SYS_TMRINTR_PEND (0) -#define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5)) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CFG_SYS_UDELAY_BASE (MMAP_TMR0) +#define CFG_SYS_TMR_BASE (MMAP_TMR3) +#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr) +#define CFG_SYS_TMRINTR_NO (INT_TMR3) +#define CFG_SYS_TMRINTR_MASK (INT_ISR_INT24) +#define CFG_SYS_TMRINTR_PEND (0) +#define CFG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5)) +#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #endif /* CONFIG_M5272 */ @@ -146,21 +146,21 @@ #include <asm/immap_5275.h> #include <asm/m5275.h> -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) +#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (192) +#define CFG_SYS_INTR_BASE (MMAP_INTC0) +#define CFG_SYS_NUM_IRQS (192) /* Timer */ #ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) -#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (0x1E) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CFG_SYS_TMR_BASE (MMAP_DTMR3) +#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0) +#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3) +#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) +#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) +#define CFG_SYS_TMRINTR_PRI (0x1E) +#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #endif /* CONFIG_M5275 */ @@ -168,21 +168,21 @@ #include <asm/immap_5282.h> #include <asm/m5282.h> -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) +#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) +#define CFG_SYS_INTR_BASE (MMAP_INTC0) +#define CFG_SYS_NUM_IRQS (128) /* Timer */ #ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) -#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) -#define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CFG_SYS_TMR_BASE (MMAP_DTMR3) +#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0) +#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3) +#define CFG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3) +#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) +#define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ +#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #endif /* CONFIG_M5282 */ @@ -190,23 +190,23 @@ #include <asm/immap_5307.h> #include <asm/m5307.h> -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ +#define CFG_SYS_UART_BASE (MMAP_UART0 + \ (CFG_SYS_UART_PORT * 0x40)) -#define CONFIG_SYS_INTR_BASE (MMAP_INTC) -#define CONFIG_SYS_NUM_IRQS (64) +#define CFG_SYS_INTR_BASE (MMAP_INTC) +#define CFG_SYS_NUM_IRQS (64) /* Timer */ #ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \ - (CONFIG_SYS_INTR_BASE))->ipr) -#define CONFIG_SYS_TMRINTR_NO (31) -#define CONFIG_SYS_TMRINTR_MASK (0x00000400) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \ +#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CFG_SYS_TMR_BASE (MMAP_DTMR1) +#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *) \ + (CFG_SYS_INTR_BASE))->ipr) +#define CFG_SYS_TMRINTR_NO (31) +#define CFG_SYS_TMRINTR_MASK (0x00000400) +#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) +#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \ MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #endif /* CONFIG_M5307 */ @@ -214,44 +214,44 @@ #include <asm/immap_5301x.h> #include <asm/m5301x.h> -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) +#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) /* Timer */ #ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) -#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (6) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CFG_SYS_TMR_BASE (MMAP_DTMR1) +#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0) +#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1) +#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) +#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) +#define CFG_SYS_TMRINTR_PRI (6) +#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) +#define CFG_SYS_INTR_BASE (MMAP_INTC0) +#define CFG_SYS_NUM_IRQS (128) #endif /* CONFIG_M5301x */ #if defined(CONFIG_M5329) || defined(CONFIG_M5373) #include <asm/immap_5329.h> #include <asm/m5329.h> -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) +#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) /* Timer */ #ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) -#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (6) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CFG_SYS_TMR_BASE (MMAP_DTMR1) +#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0) +#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1) +#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) +#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) +#define CFG_SYS_TMRINTR_PRI (6) +#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) +#define CFG_SYS_INTR_BASE (MMAP_INTC0) +#define CFG_SYS_NUM_IRQS (128) #endif /* CONFIG_M5329 && CONFIG_M5373 */ #if defined(CONFIG_M54418) @@ -259,10 +259,10 @@ #include <asm/m5441x.h> #if (CFG_SYS_UART_PORT < 4) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ +#define CFG_SYS_UART_BASE (MMAP_UART0 + \ (CFG_SYS_UART_PORT * 0x4000)) #else -#define CONFIG_SYS_UART_BASE (MMAP_UART4 + \ +#define CFG_SYS_UART_BASE (MMAP_UART4 + \ ((CFG_SYS_UART_PORT - 4) * 0x4000)) #endif @@ -270,18 +270,18 @@ /* Timer */ #ifdef CONFIG_MCFTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) -#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) -#define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) -#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (6) -#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CFG_SYS_TMR_BASE (MMAP_DTMR1) +#define CFG_SYS_TMRPND_REG (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0) +#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1) +#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) +#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) +#define CFG_SYS_TMRINTR_PRI (6) +#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (192) +#define CFG_SYS_INTR_BASE (MMAP_INTC0) +#define CFG_SYS_NUM_IRQS (192) #endif /* CONFIG_M54418 */ @@ -304,21 +304,21 @@ #define FEC1_TX_INIT 31 #endif -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100)) +#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100)) #ifdef CONFIG_SLTTMR -#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) -#define CONFIG_SYS_TMR_BASE (MMAP_SLT0) -#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) -#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0) -#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) -#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) -#define CONFIG_SYS_TMRINTR_PRI (0x1E) -#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) +#define CFG_SYS_UDELAY_BASE (MMAP_SLT1) +#define CFG_SYS_TMR_BASE (MMAP_SLT0) +#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0) +#define CFG_SYS_TMRINTR_NO (INT0_HI_SLT0) +#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) +#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK) +#define CFG_SYS_TMRINTR_PRI (0x1E) +#define CFG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) #endif -#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) -#define CONFIG_SYS_NUM_IRQS (128) +#define CFG_SYS_INTR_BASE (MMAP_INTC0) +#define CFG_SYS_NUM_IRQS (128) #ifdef CONFIG_PCI #define CFG_SYS_PCI_BAR0 (0x40000000) diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c index 4ddda69f5a3..57e5632fdb5 100644 --- a/arch/m68k/lib/cache.c +++ b/arch/m68k/lib/cache.c @@ -33,12 +33,12 @@ void icache_enable(void) *cf_icache_status = 1; -#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) +#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E) __asm__ __volatile__("movec %0, %%acr2"::"r"(CFG_SYS_CACHE_ACR2)); - __asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3)); -#if defined(CONFIG_CF_V4E) - __asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6)); - __asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7)); + __asm__ __volatile__("movec %0, %%acr3"::"r"(CFG_SYS_CACHE_ACR3)); +#if defined(CFG_CF_V4E) + __asm__ __volatile__("movec %0, %%acr6"::"r"(CFG_SYS_CACHE_ACR6)); + __asm__ __volatile__("movec %0, %%acr7"::"r"(CFG_SYS_CACHE_ACR7)); #endif #else __asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0)); @@ -55,10 +55,10 @@ void icache_disable(void) *cf_icache_status = 0; icache_invalid(); -#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) +#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E) __asm__ __volatile__("movec %0, %%acr2"::"r"(temp)); __asm__ __volatile__("movec %0, %%acr3"::"r"(temp)); -#if defined(CONFIG_CF_V4E) +#if defined(CFG_CF_V4E) __asm__ __volatile__("movec %0, %%acr6"::"r"(temp)); __asm__ __volatile__("movec %0, %%acr7"::"r"(temp)); #endif @@ -88,12 +88,12 @@ void dcache_enable(void) dcache_invalid(); *cf_dcache_status = 1; -#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) +#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E) __asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0)); __asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1)); -#if defined(CONFIG_CF_V4E) - __asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4)); - __asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5)); +#if defined(CFG_CF_V4E) + __asm__ __volatile__("movec %0, %%acr4"::"r"(CFG_SYS_CACHE_ACR4)); + __asm__ __volatile__("movec %0, %%acr5"::"r"(CFG_SYS_CACHE_ACR5)); #endif #endif @@ -109,10 +109,10 @@ void dcache_disable(void) __asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); -#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) +#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E) __asm__ __volatile__("movec %0, %%acr0"::"r"(temp)); __asm__ __volatile__("movec %0, %%acr1"::"r"(temp)); -#if defined(CONFIG_CF_V4E) +#if defined(CFG_CF_V4E) __asm__ __volatile__("movec %0, %%acr4"::"r"(temp)); __asm__ __volatile__("movec %0, %%acr5"::"r"(temp)); #endif @@ -121,7 +121,7 @@ void dcache_disable(void) void dcache_invalid(void) { -#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) +#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E) u32 temp; temp = CFG_SYS_DCACHE_INV; diff --git a/arch/m68k/lib/interrupts.c b/arch/m68k/lib/interrupts.c index 1caef61d20e..799daab5612 100644 --- a/arch/m68k/lib/interrupts.c +++ b/arch/m68k/lib/interrupts.c @@ -14,7 +14,7 @@ #include <asm/immap.h> #include <asm/ptrace.h> -#define NR_IRQS (CONFIG_SYS_NUM_IRQS) +#define NR_IRQS (CFG_SYS_NUM_IRQS) /* * Interrupt vector functions. diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c index cd7437b3e22..2ce69088d94 100644 --- a/arch/m68k/lib/time.c +++ b/arch/m68k/lib/time.c @@ -21,23 +21,23 @@ DECLARE_GLOBAL_DATA_PTR; static volatile ulong timestamp = 0; -#ifndef CONFIG_SYS_WATCHDOG_FREQ -#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2) +#ifndef CFG_SYS_WATCHDOG_FREQ +#define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2) #endif #if defined(CONFIG_MCFTMR) -#ifndef CONFIG_SYS_UDELAY_BASE +#ifndef CFG_SYS_UDELAY_BASE # error "uDelay base not defined!" #endif -#if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK) +#if !defined(CFG_SYS_TMR_BASE) || !defined(CFG_SYS_INTR_BASE) || !defined(CFG_SYS_TMRINTR_NO) || !defined(CFG_SYS_TMRINTR_MASK) # error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!" #endif extern void dtimer_intr_setup(void); void __udelay(unsigned long usec) { - volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_UDELAY_BASE); + volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_UDELAY_BASE); uint start, now, tmp; while (usec > 0) { @@ -52,7 +52,7 @@ void __udelay(unsigned long usec) timerp->tcn = 0; /* set period to 1 us */ timerp->tmr = - CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR | + CFG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR | DTIM_DTMR_RST_EN; start = now = timerp->tcn; @@ -63,15 +63,15 @@ void __udelay(unsigned long usec) void dtimer_interrupt(void *not_used) { - volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE); + volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_TMR_BASE); /* check for timer interrupt asserted */ - if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) { + if ((CFG_SYS_TMRPND_REG & CFG_SYS_TMRINTR_MASK) == CFG_SYS_TMRINTR_PEND) { timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF); timestamp++; #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) - if (CONFIG_SYS_WATCHDOG_FREQ && (timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) { + if (CFG_SYS_WATCHDOG_FREQ && (timestamp % (CFG_SYS_WATCHDOG_FREQ)) == 0) { schedule(); } #endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ @@ -81,7 +81,7 @@ void dtimer_interrupt(void *not_used) int timer_init(void) { - volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE); + volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_TMR_BASE); timestamp = 0; @@ -92,7 +92,7 @@ int timer_init(void) timerp->tmr = DTIM_DTMR_RST_RST; /* initialize and enable timer interrupt */ - irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0); + irq_install_handler(CFG_SYS_TMRINTR_NO, dtimer_interrupt, 0); timerp->tcn = 0; timerp->trr = 1000; /* Interrupt every ms */ @@ -100,7 +100,7 @@ int timer_init(void) dtimer_intr_setup(); /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ - timerp->tmr = CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | + timerp->tmr = CFG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN; return 0; diff --git a/arch/mips/mach-mtmips/mt7621/spl/start.S b/arch/mips/mach-mtmips/mt7621/spl/start.S index 7063f32610b..d2f9c031cba 100644 --- a/arch/mips/mach-mtmips/mt7621/spl/start.S +++ b/arch/mips/mach-mtmips/mt7621/spl/start.S @@ -17,8 +17,8 @@ #include "../mt7621.h" #include "dram.h" -#ifndef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \ +#ifndef CFG_SYS_INIT_SP_ADDR +#define CFG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \ CFG_SYS_INIT_SP_OFFSET) #endif @@ -31,7 +31,7 @@ .macro setup_stack_gd li t0, -16 - PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR + PTR_LI t1, CFG_SYS_INIT_SP_ADDR and sp, t1, t0 # force 16 byte alignment PTR_SUBU \ sp, sp, GD_SIZE # reserve space for gd @@ -201,7 +201,7 @@ ENTRY(_start) #if CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F) /* Set malloc base */ - li t0, (CONFIG_SYS_INIT_SP_ADDR + 15) & (~15) + li t0, (CFG_SYS_INIT_SP_ADDR + 15) & (~15) PTR_S t0, GD_MALLOC_BASE(k0) # gd->malloc_base offset #endif diff --git a/arch/powerpc/cpu/mpc83xx/bats/bats.h b/arch/powerpc/cpu/mpc83xx/bats/bats.h index f0754c2351e..2629cd5eab8 100644 --- a/arch/powerpc/cpu/mpc83xx/bats/bats.h +++ b/arch/powerpc/cpu/mpc83xx/bats/bats.h @@ -1,223 +1,223 @@ #ifdef CONFIG_BAT0 -#define CONFIG_SYS_IBAT0L (\ +#define CFG_SYS_IBAT0L (\ (CONFIG_BAT0_BASE) |\ (CONFIG_BAT0_PAGE_PROTECTION) |\ (CONFIG_BAT0_WIMG_ICACHE) \ ) -#define CONFIG_SYS_IBAT0U (\ +#define CFG_SYS_IBAT0U (\ (CONFIG_BAT0_BASE) |\ (CONFIG_BAT0_LENGTH) |\ (CONFIG_BAT0_VALID_BITS) \ ) -#define CONFIG_SYS_DBAT0L (\ +#define CFG_SYS_DBAT0L (\ (CONFIG_BAT0_BASE) |\ (CONFIG_BAT0_PAGE_PROTECTION) |\ (CONFIG_BAT0_WIMG_DCACHE) \ ) -#define CONFIG_SYS_DBAT0U (\ +#define CFG_SYS_DBAT0U (\ (CONFIG_BAT0_BASE) |\ (CONFIG_BAT0_LENGTH) |\ (CONFIG_BAT0_VALID_BITS) \ ) #else -#define CONFIG_SYS_IBAT0L (0) -#define CONFIG_SYS_IBAT0U (0) -#define CONFIG_SYS_DBAT0L (0) -#define CONFIG_SYS_DBAT0U (0) +#define CFG_SYS_IBAT0L (0) +#define CFG_SYS_IBAT0U (0) +#define CFG_SYS_DBAT0L (0) +#define CFG_SYS_DBAT0U (0) #endif /* CONFIG_BAT0 */ #ifdef CONFIG_BAT1 -#define CONFIG_SYS_IBAT1L (\ +#define CFG_SYS_IBAT1L (\ (CONFIG_BAT1_BASE) |\ (CONFIG_BAT1_PAGE_PROTECTION) |\ (CONFIG_BAT1_WIMG_ICACHE) \ ) -#define CONFIG_SYS_IBAT1U (\ +#define CFG_SYS_IBAT1U (\ (CONFIG_BAT1_BASE) |\ (CONFIG_BAT1_LENGTH) |\ (CONFIG_BAT1_VALID_BITS) \ ) -#define CONFIG_SYS_DBAT1L (\ +#define CFG_SYS_DBAT1L (\ (CONFIG_BAT1_BASE) |\ (CONFIG_BAT1_PAGE_PROTECTION) |\ (CONFIG_BAT1_WIMG_DCACHE) \ ) -#define CONFIG_SYS_DBAT1U (\ +#define CFG_SYS_DBAT1U (\ (CONFIG_BAT1_BASE) |\ (CONFIG_BAT1_LENGTH) |\ (CONFIG_BAT1_VALID_BITS) \ ) #else -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_DBAT1L (0) -#define CONFIG_SYS_DBAT1U (0) +#define CFG_SYS_IBAT1L (0) +#define CFG_SYS_IBAT1U (0) +#define CFG_SYS_DBAT1L (0) +#define CFG_SYS_DBAT1U (0) #endif /* CONFIG_BAT1 */ #ifdef CONFIG_BAT2 -#define CONFIG_SYS_IBAT2L (\ +#define CFG_SYS_IBAT2L (\ (CONFIG_BAT2_BASE) |\ (CONFIG_BAT2_PAGE_PROTECTION) |\ (CONFIG_BAT2_WIMG_ICACHE) \ ) -#define CONFIG_SYS_IBAT2U (\ +#define CFG_SYS_IBAT2U (\ (CONFIG_BAT2_BASE) |\ (CONFIG_BAT2_LENGTH) |\ (CONFIG_BAT2_VALID_BITS) \ ) -#define CONFIG_SYS_DBAT2L (\ +#define CFG_SYS_DBAT2L (\ (CONFIG_BAT2_BASE) |\ (CONFIG_BAT2_PAGE_PROTECTION) |\ (CONFIG_BAT2_WIMG_DCACHE) \ ) -#define CONFIG_SYS_DBAT2U (\ +#define CFG_SYS_DBAT2U (\ (CONFIG_BAT2_BASE) |\ (CONFIG_BAT2_LENGTH) |\ (CONFIG_BAT2_VALID_BITS) \ ) #else -#define CONFIG_SYS_IBAT2L (0) -#define CONFIG_SYS_IBAT2U (0) -#define CONFIG_SYS_DBAT2L (0) -#define CONFIG_SYS_DBAT2U (0) +#define CFG_SYS_IBAT2L (0) +#define CFG_SYS_IBAT2U (0) +#define CFG_SYS_DBAT2L (0) +#define CFG_SYS_DBAT2U (0) #endif /* CONFIG_BAT2 */ #ifdef CONFIG_BAT3 -#define CONFIG_SYS_IBAT3L (\ +#define CFG_SYS_IBAT3L (\ (CONFIG_BAT3_BASE) |\ (CONFIG_BAT3_PAGE_PROTECTION) |\ (CONFIG_BAT3_WIMG_ICACHE) \ ) -#define CONFIG_SYS_IBAT3U (\ +#define CFG_SYS_IBAT3U (\ (CONFIG_BAT3_BASE) |\ (CONFIG_BAT3_LENGTH) |\ (CONFIG_BAT3_VALID_BITS) \ ) -#define CONFIG_SYS_DBAT3L (\ +#define CFG_SYS_DBAT3L (\ (CONFIG_BAT3_BASE) |\ (CONFIG_BAT3_PAGE_PROTECTION) |\ (CONFIG_BAT3_WIMG_DCACHE) \ ) -#define CONFIG_SYS_DBAT3U (\ +#define CFG_SYS_DBAT3U (\ (CONFIG_BAT3_BASE) |\ (CONFIG_BAT3_LENGTH) |\ (CONFIG_BAT3_VALID_BITS) \ ) #else -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_DBAT3L (0) -#define CONFIG_SYS_DBAT3U (0) +#define CFG_SYS_IBAT3L (0) +#define CFG_SYS_IBAT3U (0) +#define CFG_SYS_DBAT3L (0) +#define CFG_SYS_DBAT3U (0) #endif /* CONFIG_BAT3 */ #ifdef CONFIG_BAT4 -#define CONFIG_SYS_IBAT4L (\ +#define CFG_SYS_IBAT4L (\ (CONFIG_BAT4_BASE) |\ (CONFIG_BAT4_PAGE_PROTECTION) |\ (CONFIG_BAT4_WIMG_ICACHE) \ ) -#define CONFIG_SYS_IBAT4U (\ +#define CFG_SYS_IBAT4U (\ (CONFIG_BAT4_BASE) |\ (CONFIG_BAT4_LENGTH) |\ (CONFIG_BAT4_VALID_BITS) \ ) -#define CONFIG_SYS_DBAT4L (\ +#define CFG_SYS_DBAT4L (\ (CONFIG_BAT4_BASE) |\ (CONFIG_BAT4_PAGE_PROTECTION) |\ (CONFIG_BAT4_WIMG_DCACHE) \ ) -#define CONFIG_SYS_DBAT4U (\ +#define CFG_SYS_DBAT4U (\ (CONFIG_BAT4_BASE) |\ (CONFIG_BAT4_LENGTH) |\ (CONFIG_BAT4_VALID_BITS) \ ) #else -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#define CONFIG_SYS_DBAT4L (0) -#define CONFIG_SYS_DBAT4U (0) +#define CFG_SYS_IBAT4L (0) +#define CFG_SYS_IBAT4U (0) +#define CFG_SYS_DBAT4L (0) +#define CFG_SYS_DBAT4U (0) #endif /* CONFIG_BAT4 */ #ifdef CONFIG_BAT5 -#define CONFIG_SYS_IBAT5L (\ +#define CFG_SYS_IBAT5L (\ (CONFIG_BAT5_BASE) |\ (CONFIG_BAT5_PAGE_PROTECTION) |\ (CONFIG_BAT5_WIMG_ICACHE) \ ) -#define CONFIG_SYS_IBAT5U (\ +#define CFG_SYS_IBAT5U (\ (CONFIG_BAT5_BASE) |\ (CONFIG_BAT5_LENGTH) |\ (CONFIG_BAT5_VALID_BITS) \ ) -#define CONFIG_SYS_DBAT5L (\ +#define CFG_SYS_DBAT5L (\ (CONFIG_BAT5_BASE) |\ (CONFIG_BAT5_PAGE_PROTECTION) |\ (CONFIG_BAT5_WIMG_DCACHE) \ ) -#define CONFIG_SYS_DBAT5U (\ +#define CFG_SYS_DBAT5U (\ (CONFIG_BAT5_BASE) |\ (CONFIG_BAT5_LENGTH) |\ (CONFIG_BAT5_VALID_BITS) \ ) #else -#define CONFIG_SYS_IBAT5L (0) -#define CONFIG_SYS_IBAT5U (0) -#define CONFIG_SYS_DBAT5L (0) -#define CONFIG_SYS_DBAT5U (0) +#define CFG_SYS_IBAT5L (0) +#define CFG_SYS_IBAT5U (0) +#define CFG_SYS_DBAT5L (0) +#define CFG_SYS_DBAT5U (0) #endif /* CONFIG_BAT5 */ #ifdef CONFIG_BAT6 -#define CONFIG_SYS_IBAT6L (\ +#define CFG_SYS_IBAT6L (\ (CONFIG_BAT6_BASE) |\ (CONFIG_BAT6_PAGE_PROTECTION) |\ (CONFIG_BAT6_WIMG_ICACHE) \ ) -#define CONFIG_SYS_IBAT6U (\ +#define CFG_SYS_IBAT6U (\ (CONFIG_BAT6_BASE) |\ (CONFIG_BAT6_LENGTH) |\ (CONFIG_BAT6_VALID_BITS) \ ) -#define CONFIG_SYS_DBAT6L (\ +#define CFG_SYS_DBAT6L (\ (CONFIG_BAT6_BASE) |\ (CONFIG_BAT6_PAGE_PROTECTION) |\ (CONFIG_BAT6_WIMG_DCACHE) \ ) -#define CONFIG_SYS_DBAT6U (\ +#define CFG_SYS_DBAT6U (\ (CONFIG_BAT6_BASE) |\ (CONFIG_BAT6_LENGTH) |\ (CONFIG_BAT6_VALID_BITS) \ ) #else -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_DBAT6L (0) -#define CONFIG_SYS_DBAT6U (0) +#define CFG_SYS_IBAT6L (0) +#define CFG_SYS_IBAT6U (0) +#define CFG_SYS_DBAT6L (0) +#define CFG_SYS_DBAT6U (0) #endif /* CONFIG_BAT6 */ #ifdef CONFIG_BAT7 -#define CONFIG_SYS_IBAT7L (\ +#define CFG_SYS_IBAT7L (\ (CONFIG_BAT7_BASE) |\ (CONFIG_BAT7_PAGE_PROTECTION) |\ (CONFIG_BAT7_WIMG_ICACHE) \ ) -#define CONFIG_SYS_IBAT7U (\ +#define CFG_SYS_IBAT7U (\ (CONFIG_BAT7_BASE) |\ (CONFIG_BAT7_LENGTH) |\ (CONFIG_BAT7_VALID_BITS) \ ) -#define CONFIG_SYS_DBAT7L (\ +#define CFG_SYS_DBAT7L (\ (CONFIG_BAT7_BASE) |\ (CONFIG_BAT7_PAGE_PROTECTION) |\ (CONFIG_BAT7_WIMG_DCACHE) \ ) -#define CONFIG_SYS_DBAT7U (\ +#define CFG_SYS_DBAT7U (\ (CONFIG_BAT7_BASE) |\ (CONFIG_BAT7_LENGTH) |\ (CONFIG_BAT7_VALID_BITS) \ ) #else -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L (0) -#define CONFIG_SYS_DBAT7U (0) +#define CFG_SYS_IBAT7L (0) +#define CFG_SYS_IBAT7U (0) +#define CFG_SYS_DBAT7L (0) +#define CFG_SYS_DBAT7U (0) #endif /* CONFIG_BAT7 */ diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 63c2729411c..2af5c89ae52 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -208,24 +208,24 @@ void cpu_init_f (volatile immap_t * im) init_early_memctl_regs(); /* Local Access window setup */ -#if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM) - im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM; - im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM; +#if defined(CFG_SYS_LBLAWBAR0_PRELIM) && defined(CFG_SYS_LBLAWAR0_PRELIM) + im->sysconf.lblaw[0].bar = CFG_SYS_LBLAWBAR0_PRELIM; + im->sysconf.lblaw[0].ar = CFG_SYS_LBLAWAR0_PRELIM; #else -#error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined +#error CFG_SYS_LBLAWBAR0_PRELIM & CFG_SYS_LBLAWAR0_PRELIM must be defined #endif -#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM) - im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM; - im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM; +#if defined(CFG_SYS_LBLAWBAR1_PRELIM) && defined(CFG_SYS_LBLAWAR1_PRELIM) + im->sysconf.lblaw[1].bar = CFG_SYS_LBLAWBAR1_PRELIM; + im->sysconf.lblaw[1].ar = CFG_SYS_LBLAWAR1_PRELIM; #endif -#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM) - im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM; - im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM; +#if defined(CFG_SYS_LBLAWBAR2_PRELIM) && defined(CFG_SYS_LBLAWAR2_PRELIM) + im->sysconf.lblaw[2].bar = CFG_SYS_LBLAWBAR2_PRELIM; + im->sysconf.lblaw[2].ar = CFG_SYS_LBLAWAR2_PRELIM; #endif -#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM) - im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM; - im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM; +#if defined(CFG_SYS_LBLAWBAR3_PRELIM) && defined(CFG_SYS_LBLAWAR3_PRELIM) + im->sysconf.lblaw[3].bar = CFG_SYS_LBLAWBAR3_PRELIM; + im->sysconf.lblaw[3].ar = CFG_SYS_LBLAWAR3_PRELIM; #endif #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM) im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM; diff --git a/arch/powerpc/cpu/mpc83xx/hid/hid.h b/arch/powerpc/cpu/mpc83xx/hid/hid.h index 9f5260c012c..089d1d77f0b 100644 --- a/arch/powerpc/cpu/mpc83xx/hid/hid.h +++ b/arch/powerpc/cpu/mpc83xx/hid/hid.h @@ -1,4 +1,4 @@ -#define CONFIG_SYS_HID0_FINAL ( \ +#define CFG_SYS_HID0_FINAL ( \ CONFIG_HID0_FINAL_ABE_BIT |\ CONFIG_HID0_FINAL_CLKOUT |\ CONFIG_HID0_FINAL_DCE_BIT |\ @@ -24,7 +24,7 @@ CONFIG_HID0_FINAL_SLEEP_BIT \ ) -#define CONFIG_SYS_HID0_INIT ( \ +#define CFG_SYS_HID0_INIT ( \ CONFIG_HID0_INIT_ABE_BIT |\ CONFIG_HID0_INIT_CLKOUT |\ CONFIG_HID0_INIT_DCE_BIT |\ @@ -50,12 +50,12 @@ #ifdef CONFIG_TARGET_IDS8313 /* IDS8313 defines a reserved bit; keep to not break compatibility */ -#define CONFIG_HID2_SPECIAL 0x00020000 +#define CFG_HID2_SPECIAL 0x00020000 #else -#define CONFIG_HID2_SPECIAL 0x0 +#define CFG_HID2_SPECIAL 0x0 #endif -#define CONFIG_SYS_HID2 ( \ +#define CFG_SYS_HID2 ( \ CONFIG_HID2_LET_BIT |\ CONFIG_HID2_IFEB_BIT |\ CONFIG_HID2_MESISTATE_BIT |\ @@ -68,5 +68,5 @@ CONFIG_HID2_IWLCK |\ CONFIG_HID2_ICWP_BIT |\ CONFIG_HID2_DWLCK |\ - CONFIG_HID2_SPECIAL \ + CFG_HID2_SPECIAL \ ) diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h index 0f342678918..7f8787ffb0d 100644 --- a/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h +++ b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h @@ -1,4 +1,4 @@ -#define CONFIG_SYS_HRCW_LOW (\ +#define CFG_SYS_HRCW_LOW (\ (CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\ (CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\ (CONFIG_SYSTEM_PLL_VCO_DIV << (31 - 3)) |\ @@ -9,7 +9,7 @@ (CONFIG_QUICC_MULT_FACTOR << (31 - 31)) \ ) -#define CONFIG_SYS_HRCW_HIGH (\ +#define CFG_SYS_HRCW_HIGH (\ (CONFIG_PCI_HOST_MODE << (31 - 0)) |\ (CONFIG_PCI_64BIT_MODE << (31 - 1)) |\ (CONFIG_PCI_INT_ARBITER1 << (31 - 2)) |\ diff --git a/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h b/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h index 6972afcc2c7..082b2b9c9a5 100644 --- a/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h +++ b/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h @@ -1,55 +1,55 @@ #if defined(CONFIG_LBLAW0) -#define CONFIG_SYS_LBLAWBAR0_PRELIM \ +#define CFG_SYS_LBLAWBAR0_PRELIM \ CONFIG_LBLAW0_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (\ +#define CFG_SYS_LBLAWAR0_PRELIM (\ CONFIG_LBLAW0_ENABLE_BIT |\ CONFIG_LBLAW0_LENGTH \ ) #endif #if defined(CONFIG_LBLAW1) -#define CONFIG_SYS_LBLAWBAR1_PRELIM \ +#define CFG_SYS_LBLAWBAR1_PRELIM \ CONFIG_LBLAW1_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (\ +#define CFG_SYS_LBLAWAR1_PRELIM (\ CONFIG_LBLAW1_ENABLE_BIT |\ CONFIG_LBLAW1_LENGTH \ ) #endif #if defined(CONFIG_LBLAW2) -#define CONFIG_SYS_LBLAWBAR2_PRELIM \ +#define CFG_SYS_LBLAWBAR2_PRELIM \ CONFIG_LBLAW2_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (\ +#define CFG_SYS_LBLAWAR2_PRELIM (\ CONFIG_LBLAW2_ENABLE_BIT |\ CONFIG_LBLAW2_LENGTH \ ) #endif #if defined(CONFIG_LBLAW3) -#define CONFIG_SYS_LBLAWBAR3_PRELIM \ +#define CFG_SYS_LBLAWBAR3_PRELIM \ CONFIG_LBLAW3_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (\ +#define CFG_SYS_LBLAWAR3_PRELIM (\ CONFIG_LBLAW3_ENABLE_BIT |\ CONFIG_LBLAW3_LENGTH \ ) #endif #ifdef CONFIG_NAND_LBLAWBAR_PRELIM_0 -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM +#define CFG_SYS_NAND_LBLAWBAR_PRELIM CFG_SYS_LBLAWBAR0_PRELIM +#define CFG_SYS_NAND_LBLAWAR_PRELIM CFG_SYS_LBLAWAR0_PRELIM #endif #ifdef CONFIG_NAND_LBLAWBAR_PRELIM_1 -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM +#define CFG_SYS_NAND_LBLAWBAR_PRELIM CFG_SYS_LBLAWBAR1_PRELIM +#define CFG_SYS_NAND_LBLAWAR_PRELIM CFG_SYS_LBLAWAR1_PRELIM #endif #ifdef CONFIG_NAND_LBLAWBAR_PRELIM_2 -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR2_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR2_PRELIM +#define CFG_SYS_NAND_LBLAWBAR_PRELIM CFG_SYS_LBLAWBAR2_PRELIM +#define CFG_SYS_NAND_LBLAWAR_PRELIM CFG_SYS_LBLAWAR2_PRELIM #endif #ifdef CONFIG_NAND_LBLAWBAR_PRELIM_3 -#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR3_PRELIM -#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR3_PRELIM +#define CFG_SYS_NAND_LBLAWBAR_PRELIM CFG_SYS_LBLAWBAR3_PRELIM +#define CFG_SYS_NAND_LBLAWAR_PRELIM CFG_SYS_LBLAWAR3_PRELIM #endif diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 4f982b8303a..6da8fc4381d 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -66,8 +66,8 @@ void board_add_ram_info(int use_default) } #ifdef CONFIG_SPD_EEPROM -#ifndef CONFIG_SYS_READ_SPD -#define CONFIG_SYS_READ_SPD i2c_read +#ifndef CFG_SYS_READ_SPD +#define CFG_SYS_READ_SPD i2c_read #endif #ifndef SPD_EEPROM_OFFSET #define SPD_EEPROM_OFFSET 0 @@ -167,7 +167,7 @@ long int spd_sdram() isync(); /* Read SPD parameters with I2C */ - CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET, + CFG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET, SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd)); #ifdef SPD_DEBUG spd_debug(&spd); diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 7cc0383afbf..b55bfaffcae 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -73,14 +73,14 @@ void cpu_init_f (volatile immap_t * im) #if defined(CFG_SYS_NAND_BR_PRELIM) \ && defined(CFG_SYS_NAND_OR_PRELIM) \ - && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \ - && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM) + && defined(CFG_SYS_NAND_LBLAWBAR_PRELIM) \ + && defined(CFG_SYS_NAND_LBLAWAR_PRELIM) set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM); set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM); - im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM; - im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM; + im->sysconf.lblaw[0].bar = CFG_SYS_NAND_LBLAWBAR_PRELIM; + im->sysconf.lblaw[0].ar = CFG_SYS_NAND_LBLAWAR_PRELIM; #else -#error CFG_SYS_NAND_BR_PRELIM, CFG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined +#error CFG_SYS_NAND_BR_PRELIM, CFG_SYS_NAND_OR_PRELIM, CFG_SYS_NAND_LBLAWBAR_PRELIM & CFG_SYS_NAND_LBLAWAR_PRELIM must be defined #endif } diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 52326f0ec15..e3878e431fb 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -46,7 +46,7 @@ #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ !defined(CONFIG_SYS_RAMBOOT) -#define CONFIG_SYS_FLASHBOOT +#define CFG_SYS_FLASHBOOT #endif /* @@ -81,8 +81,8 @@ .fill 8,1,(((w)>> 8)&0xff); \ .fill 8,1,(((w) )&0xff) - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) - _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) + _HRCW_TABLE_ENTRY(CFG_SYS_HRCW_LOW) + _HRCW_TABLE_ENTRY(CFG_SYS_HRCW_HIGH) /* * Magic number and version string - put it after the HRCW since it @@ -180,7 +180,7 @@ _start: /* time t 0 */ bl init_e300_core -#ifdef CONFIG_SYS_FLASHBOOT +#ifdef CFG_SYS_FLASHBOOT /* Inflate flash location so it appears everywhere, calculate */ /* the absolute address in final location of the FLASH, jump */ @@ -196,7 +196,7 @@ in_flash: #if 1 /* Remapping flash with LAW0. */ bl remap_flash_by_law0 #endif -#endif /* CONFIG_SYS_FLASHBOOT */ +#endif /* CFG_SYS_FLASHBOOT */ /* setup the bats */ bl setup_bats @@ -525,18 +525,18 @@ init_e300_core: /* time t 10 */ /* - force invalidation of data and instruction caches */ /*------------------------------------------------------*/ - lis r3, CONFIG_SYS_HID0_INIT@h - ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l + lis r3, CFG_SYS_HID0_INIT@h + ori r3, r3, (CFG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l SYNC mtspr HID0, r3 - lis r3, CONFIG_SYS_HID0_FINAL@h - ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l + lis r3, CFG_SYS_HID0_FINAL@h + ori r3, r3, (CFG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l SYNC mtspr HID0, r3 - lis r3, CONFIG_SYS_HID2@h - ori r3, r3, CONFIG_SYS_HID2@l + lis r3, CFG_SYS_HID2@h + ori r3, r3, CFG_SYS_HID2@l SYNC mtspr HID2, r3 @@ -550,131 +550,131 @@ setup_bats: addis r0, r0, 0x0000 /* IBAT 0 */ - addis r4, r0, CONFIG_SYS_IBAT0L@h - ori r4, r4, CONFIG_SYS_IBAT0L@l - addis r3, r0, CONFIG_SYS_IBAT0U@h - ori r3, r3, CONFIG_SYS_IBAT0U@l + addis r4, r0, CFG_SYS_IBAT0L@h + ori r4, r4, CFG_SYS_IBAT0L@l + addis r3, r0, CFG_SYS_IBAT0U@h + ori r3, r3, CFG_SYS_IBAT0U@l mtspr IBAT0L, r4 mtspr IBAT0U, r3 /* DBAT 0 */ - addis r4, r0, CONFIG_SYS_DBAT0L@h - ori r4, r4, CONFIG_SYS_DBAT0L@l - addis r3, r0, CONFIG_SYS_DBAT0U@h - ori r3, r3, CONFIG_SYS_DBAT0U@l + addis r4, r0, CFG_SYS_DBAT0L@h + ori r4, r4, CFG_SYS_DBAT0L@l + addis r3, r0, CFG_SYS_DBAT0U@h + ori r3, r3, CFG_SYS_DBAT0U@l mtspr DBAT0L, r4 mtspr DBAT0U, r3 /* IBAT 1 */ - addis r4, r0, CONFIG_SYS_IBAT1L@h - ori r4, r4, CONFIG_SYS_IBAT1L@l - addis r3, r0, CONFIG_SYS_IBAT1U@h - ori r3, r3, CONFIG_SYS_IBAT1U@l + addis r4, r0, CFG_SYS_IBAT1L@h + ori r4, r4, CFG_SYS_IBAT1L@l + addis r3, r0, CFG_SYS_IBAT1U@h + ori r3, r3, CFG_SYS_IBAT1U@l mtspr IBAT1L, r4 mtspr IBAT1U, r3 /* DBAT 1 */ - addis r4, r0, CONFIG_SYS_DBAT1L@h - ori r4, r4, CONFIG_SYS_DBAT1L@l - addis r3, r0, CONFIG_SYS_DBAT1U@h - ori r3, r3, CONFIG_SYS_DBAT1U@l + addis r4, r0, CFG_SYS_DBAT1L@h + ori r4, r4, CFG_SYS_DBAT1L@l + addis r3, r0, CFG_SYS_DBAT1U@h + ori r3, r3, CFG_SYS_DBAT1U@l mtspr DBAT1L, r4 mtspr DBAT1U, r3 /* IBAT 2 */ - addis r4, r0, CONFIG_SYS_IBAT2L@h - ori r4, r4, CONFIG_SYS_IBAT2L@l - addis r3, r0, CONFIG_SYS_IBAT2U@h - ori r3, r3, CONFIG_SYS_IBAT2U@l + addis r4, r0, CFG_SYS_IBAT2L@h + ori r4, r4, CFG_SYS_IBAT2L@l + addis r3, r0, CFG_SYS_IBAT2U@h + ori r3, r3, CFG_SYS_IBAT2U@l mtspr IBAT2L, r4 mtspr IBAT2U, r3 /* DBAT 2 */ - addis r4, r0, CONFIG_SYS_DBAT2L@h - ori r4, r4, CONFIG_SYS_DBAT2L@l - addis r3, r0, CONFIG_SYS_DBAT2U@h - ori r3, r3, CONFIG_SYS_DBAT2U@l + addis r4, r0, CFG_SYS_DBAT2L@h + ori r4, r4, CFG_SYS_DBAT2L@l + addis r3, r0, CFG_SYS_DBAT2U@h + ori r3, r3, CFG_SYS_DBAT2U@l mtspr DBAT2L, r4 mtspr DBAT2U, r3 /* IBAT 3 */ - addis r4, r0, CONFIG_SYS_IBAT3L@h - ori r4, r4, CONFIG_SYS_IBAT3L@l - addis r3, r0, CONFIG_SYS_IBAT3U@h - ori r3, r3, CONFIG_SYS_IBAT3U@l + addis r4, r0, CFG_SYS_IBAT3L@h + ori r4, r4, CFG_SYS_IBAT3L@l + addis r3, r0, CFG_SYS_IBAT3U@h + ori r3, r3, CFG_SYS_IBAT3U@l mtspr IBAT3L, r4 mtspr IBAT3U, r3 /* DBAT 3 */ - addis r4, r0, CONFIG_SYS_DBAT3L@h - ori r4, r4, CONFIG_SYS_DBAT3L@l - addis r3, r0, CONFIG_SYS_DBAT3U@h - ori r3, r3, CONFIG_SYS_DBAT3U@l + addis r4, r0, CFG_SYS_DBAT3L@h + ori r4, r4, CFG_SYS_DBAT3L@l + addis r3, r0, CFG_SYS_DBAT3U@h + ori r3, r3, CFG_SYS_DBAT3U@l mtspr DBAT3L, r4 mtspr DBAT3U, r3 #ifdef CONFIG_HIGH_BATS /* IBAT 4 */ - addis r4, r0, CONFIG_SYS_IBAT4L@h - ori r4, r4, CONFIG_SYS_IBAT4L@l - addis r3, r0, CONFIG_SYS_IBAT4U@h - ori r3, r3, CONFIG_SYS_IBAT4U@l + addis r4, r0, CFG_SYS_IBAT4L@h + ori r4, r4, CFG_SYS_IBAT4L@l + addis r3, r0, CFG_SYS_IBAT4U@h + ori r3, r3, CFG_SYS_IBAT4U@l mtspr IBAT4L, r4 mtspr IBAT4U, r3 /* DBAT 4 */ - addis r4, r0, CONFIG_SYS_DBAT4L@h - ori r4, r4, CONFIG_SYS_DBAT4L@l - addis r3, r0, CONFIG_SYS_DBAT4U@h - ori r3, r3, CONFIG_SYS_DBAT4U@l + addis r4, r0, CFG_SYS_DBAT4L@h + ori r4, r4, CFG_SYS_DBAT4L@l + addis r3, r0, CFG_SYS_DBAT4U@h + ori r3, r3, CFG_SYS_DBAT4U@l mtspr DBAT4L, r4 mtspr DBAT4U, r3 /* IBAT 5 */ - addis r4, r0, CONFIG_SYS_IBAT5L@h - ori r4, r4, CONFIG_SYS_IBAT5L@l - addis r3, r0, CONFIG_SYS_IBAT5U@h - ori r3, r3, CONFIG_SYS_IBAT5U@l + addis r4, r0, CFG_SYS_IBAT5L@h + ori r4, r4, CFG_SYS_IBAT5L@l + addis r3, r0, CFG_SYS_IBAT5U@h + ori r3, r3, CFG_SYS_IBAT5U@l mtspr IBAT5L, r4 mtspr IBAT5U, r3 /* DBAT 5 */ - addis r4, r0, CONFIG_SYS_DBAT5L@h - ori r4, r4, CONFIG_SYS_DBAT5L@l - addis r3, r0, CONFIG_SYS_DBAT5U@h - ori r3, r3, CONFIG_SYS_DBAT5U@l + addis r4, r0, CFG_SYS_DBAT5L@h + ori r4, r4, CFG_SYS_DBAT5L@l + addis r3, r0, CFG_SYS_DBAT5U@h + ori r3, r3, CFG_SYS_DBAT5U@l mtspr DBAT5L, r4 mtspr DBAT5U, r3 /* IBAT 6 */ - addis r4, r0, CONFIG_SYS_IBAT6L@h - ori r4, r4, CONFIG_SYS_IBAT6L@l - addis r3, r0, CONFIG_SYS_IBAT6U@h - ori r3, r3, CONFIG_SYS_IBAT6U@l + addis r4, r0, CFG_SYS_IBAT6L@h + ori r4, r4, CFG_SYS_IBAT6L@l + addis r3, r0, CFG_SYS_IBAT6U@h + ori r3, r3, CFG_SYS_IBAT6U@l mtspr IBAT6L, r4 mtspr IBAT6U, r3 /* DBAT 6 */ - addis r4, r0, CONFIG_SYS_DBAT6L@h - ori r4, r4, CONFIG_SYS_DBAT6L@l - addis r3, r0, CONFIG_SYS_DBAT6U@h - ori r3, r3, CONFIG_SYS_DBAT6U@l + addis r4, r0, CFG_SYS_DBAT6L@h + ori r4, r4, CFG_SYS_DBAT6L@l + addis r3, r0, CFG_SYS_DBAT6U@h + ori r3, r3, CFG_SYS_DBAT6U@l mtspr DBAT6L, r4 mtspr DBAT6U, r3 /* IBAT 7 */ - addis r4, r0, CONFIG_SYS_IBAT7L@h - ori r4, r4, CONFIG_SYS_IBAT7L@l - addis r3, r0, CONFIG_SYS_IBAT7U@h - ori r3, r3, CONFIG_SYS_IBAT7U@l + addis r4, r0, CFG_SYS_IBAT7L@h + ori r4, r4, CFG_SYS_IBAT7L@l + addis r3, r0, CFG_SYS_IBAT7U@h + ori r3, r3, CFG_SYS_IBAT7U@l mtspr IBAT7L, r4 mtspr IBAT7U, r3 /* DBAT 7 */ - addis r4, r0, CONFIG_SYS_DBAT7L@h - ori r4, r4, CONFIG_SYS_DBAT7L@l - addis r3, r0, CONFIG_SYS_DBAT7U@h - ori r3, r3, CONFIG_SYS_DBAT7U@l + addis r4, r0, CFG_SYS_DBAT7L@h + ori r4, r4, CFG_SYS_DBAT7L@l + addis r3, r0, CFG_SYS_DBAT7U@h + ori r3, r3, CFG_SYS_DBAT7U@l mtspr DBAT7L, r4 mtspr DBAT7U, r3 #endif @@ -1095,7 +1095,7 @@ unlock_ram_in_cache: #endif /* !MINIMAL_SPL */ #endif /* CONFIG_SYS_INIT_RAM_LOCK */ -#ifdef CONFIG_SYS_FLASHBOOT +#ifdef CFG_SYS_FLASHBOOT map_flash_by_law1: /* When booting from ROM (Flash or EPROM), clear the */ /* Address Mask in OR0 so ROM appears everywhere */ @@ -1182,4 +1182,4 @@ remap_flash_by_law0: twi 0,r4,0 isync blr -#endif /* CONFIG_SYS_FLASHBOOT */ +#endif /* CFG_SYS_FLASHBOOT */ diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index f07e8ab388e..96183ac2c84 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -73,11 +73,11 @@ void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy) get_sys_info(&sysinfo); if (sysinfo.diff_sysclk == 1) { clrbits_be32(&usb_phy->pllprg[1], - CONFIG_SYS_FSL_USB_PLLPRG2_MFI); + CFG_SYS_FSL_USB_PLLPRG2_MFI); setbits_be32(&usb_phy->pllprg[1], - CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK | - CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK | - CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN); + CFG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK | + CFG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK | + CFG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN); } } #endif @@ -89,18 +89,18 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); /* Increase Disconnect Threshold by 50mV */ - xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | + xcvrprg &= ~CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | INC_DCNT_THRESHOLD_50MV; /* Enable programming of USB High speed Disconnect threshold */ - xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; + xcvrprg |= CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; out_be32(&usb_phy->port1.xcvrprg, xcvrprg); xcvrprg = in_be32(&usb_phy->port2.xcvrprg); /* Increase Disconnect Threshold by 50mV */ - xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | + xcvrprg &= ~CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | INC_DCNT_THRESHOLD_50MV; /* Enable programming of USB High speed Disconnect threshold */ - xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; + xcvrprg |= CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; out_be32(&usb_phy->port2.xcvrprg, xcvrprg); #else @@ -108,22 +108,22 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) u32 status = in_be32(&usb_phy->status1); u32 squelch_prog_rd_0_2 = - (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0) - & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; + (status >> CFG_SYS_FSL_USB_SQUELCH_PROG_RD_0) + & CFG_SYS_FSL_USB_SQUELCH_PROG_MASK; u32 squelch_prog_rd_3_5 = - (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3) - & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; + (status >> CFG_SYS_FSL_USB_SQUELCH_PROG_RD_3) + & CFG_SYS_FSL_USB_SQUELCH_PROG_MASK; setbits_be32(&usb_phy->config1, - CONFIG_SYS_FSL_USB_HS_DISCNCT_INC); + CFG_SYS_FSL_USB_HS_DISCNCT_INC); setbits_be32(&usb_phy->config2, - CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); + CFG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); - temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; + temp = squelch_prog_rd_0_2 << CFG_SYS_FSL_USB_SQUELCH_PROG_WR_3; out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); - temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; + temp = squelch_prog_rd_3_5 << CFG_SYS_FSL_USB_SQUELCH_PROG_WR_0; out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); #endif } @@ -827,7 +827,7 @@ int cpu_init_r(void) fsl_erratum_a006261_workaround(usb_phy1); #endif out_be32(&usb_phy1->usb_enable_override, - CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); + CFG_SYS_FSL_USB_ENABLE_OVERRIDE); } #endif #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE @@ -839,7 +839,7 @@ int cpu_init_r(void) fsl_erratum_a006261_workaround(usb_phy2); #endif out_be32(&usb_phy2->usb_enable_override, - CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); + CFG_SYS_FSL_USB_ENABLE_OVERRIDE); } #endif @@ -861,25 +861,25 @@ int cpu_init_r(void) struct ccsr_usb_phy __iomem *usb_phy = (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR; setbits_be32(&usb_phy->pllprg[1], - CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | - CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | - CONFIG_SYS_FSL_USB_PLLPRG2_MFI | - CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); + CFG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | + CFG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | + CFG_SYS_FSL_USB_PLLPRG2_MFI | + CFG_SYS_FSL_USB_PLLPRG2_PLL_EN); #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK usb_single_source_clk_configure(usb_phy); #endif setbits_be32(&usb_phy->port1.ctrl, - CONFIG_SYS_FSL_USB_CTRL_PHY_EN); + CFG_SYS_FSL_USB_CTRL_PHY_EN); setbits_be32(&usb_phy->port1.drvvbuscfg, - CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); + CFG_SYS_FSL_USB_DRVVBUS_CR_EN); setbits_be32(&usb_phy->port1.pwrfltcfg, - CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); + CFG_SYS_FSL_USB_PWRFLT_CR_EN); setbits_be32(&usb_phy->port2.ctrl, - CONFIG_SYS_FSL_USB_CTRL_PHY_EN); + CFG_SYS_FSL_USB_CTRL_PHY_EN); setbits_be32(&usb_phy->port2.drvvbuscfg, - CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); + CFG_SYS_FSL_USB_DRVVBUS_CR_EN); setbits_be32(&usb_phy->port2.pwrfltcfg, - CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); + CFG_SYS_FSL_USB_PWRFLT_CR_EN); #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 if (has_erratum_a006261()) diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 35142508c30..e26436bf570 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -532,7 +532,7 @@ void fdt_fixup_dma3(void *blob) int nodeoff; ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); -#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300) +#define CFG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300) #if defined(CONFIG_ARCH_T2080) u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; @@ -554,7 +554,7 @@ void fdt_fixup_dma3(void *blob) case 16: #endif nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma", - CONFIG_SYS_ELO3_DMA3); + CFG_SYS_ELO3_DMA3); if (nodeoff > 0) fdt_status_disabled(blob, nodeoff); else @@ -616,11 +616,11 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) fdt_add_enet_stashing(blob); -#ifndef CONFIG_FSL_TBCLK_EXTRA_DIV -#define CONFIG_FSL_TBCLK_EXTRA_DIV 1 +#ifndef CFG_FSL_TBCLK_EXTRA_DIV +#define CFG_FSL_TBCLK_EXTRA_DIV 1 #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV, + "timebase-frequency", get_tbclk() / CFG_FSL_TBCLK_EXTRA_DIV, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index 18790921dd7..4b8844a4d96 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -255,14 +255,14 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl) } #endif -#define CONFIG_SYS_MAX_PCI_EPS 8 +#define CFG_SYS_MAX_PCI_EPS 8 static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat, int ep_liodn_start) { int off, pci_idx = 0, pci_cnt = 0, i, rc; const uint32_t *base_liodn; - uint32_t liodn_offs[CONFIG_SYS_MAX_PCI_EPS + 1] = { 0 }; + uint32_t liodn_offs[CFG_SYS_MAX_PCI_EPS + 1] = { 0 }; /* * Count the number of pci nodes. @@ -282,7 +282,7 @@ static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat, path, fdt_strerror(rc)); continue; } - for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++) + for (i = 0; i < CFG_SYS_MAX_PCI_EPS; i++) liodn_offs[i + 1] = ep_liodn_start + i * pci_cnt + pci_idx - *base_liodn; rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list", diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 1c051d18980..8e1f6c964d3 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -240,8 +240,8 @@ int pamu_init(void) spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES; /* Allocate space for Primary PAACT Table */ -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_PPAACT_ADDR)) - ppaact = (void *)CONFIG_SPL_PPAACT_ADDR; +#if (defined(CONFIG_SPL_BUILD) && defined(CFG_SPL_PPAACT_ADDR)) + ppaact = (void *)CFG_SPL_PPAACT_ADDR; #else ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size); if (!ppaact) @@ -250,8 +250,8 @@ int pamu_init(void) memset(ppaact, 0, ppaact_size); /* Allocate space for Secondary PAACT Table */ -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SPAACT_ADDR)) - sec = (void *)CONFIG_SPL_SPAACT_ADDR; +#if (defined(CONFIG_SPL_BUILD) && defined(CFG_SPL_SPAACT_ADDR)) + sec = (void *)CFG_SPL_SPAACT_ADDR; #else sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size); if (!sec) @@ -266,7 +266,7 @@ int pamu_init(void) spaact_lim = spaact_phys + spaact_size; /* Configure all PAMU's */ - for (i = 0; i < CONFIG_NUM_PAMU; i++) { + for (i = 0; i < CFG_NUM_PAMU; i++) { regs = (struct ccsr_pamu *)base_addr; out_be32(®s->ppbah, ppaact_phys >> 32); @@ -293,7 +293,7 @@ void pamu_enable(void) { u32 i = 0; u32 base_addr = CFG_SYS_PAMU_ADDR; - for (i = 0; i < CONFIG_NUM_PAMU; i++) { + for (i = 0; i < CFG_NUM_PAMU; i++) { setbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE); sync(); @@ -307,7 +307,7 @@ void pamu_reset(void) u32 base_addr = CFG_SYS_PAMU_ADDR; struct ccsr_pamu *regs; - for (i = 0; i < CONFIG_NUM_PAMU; i++) { + for (i = 0; i < CFG_NUM_PAMU; i++) { regs = (struct ccsr_pamu *)base_addr; /* Clear PPAACT Base register */ out_be32(®s->ppbah, 0); @@ -331,7 +331,7 @@ void pamu_disable(void) u32 base_addr = CFG_SYS_PAMU_ADDR; - for (i = 0; i < CONFIG_NUM_PAMU; i++) { + for (i = 0; i < CFG_NUM_PAMU; i++) { clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE); sync(); base_addr += PAMU_OFFSET; diff --git a/arch/powerpc/include/asm/fsl_pamu.h b/arch/powerpc/include/asm/fsl_pamu.h index 07e822b796e..d0d33fd1636 100644 --- a/arch/powerpc/include/asm/fsl_pamu.h +++ b/arch/powerpc/include/asm/fsl_pamu.h @@ -6,7 +6,7 @@ #ifndef __PAMU_H #define __PAMU_H -#define CONFIG_NUM_PAMU 16 +#define CFG_NUM_PAMU 16 #define NUM_PPAACT_ENTRIES 512 #define NUM_SPAACT_ENTRIES 256 diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 236098e718e..221f9d842a8 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -41,10 +41,10 @@ * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init * due to space crunch on CPC and thus malloc will not work. */ -#define CONFIG_SPL_PPAACT_ADDR 0x2e000000 -#define CONFIG_SPL_SPAACT_ADDR 0x2f000000 -#define CONFIG_SPL_JR0_LIODN_S 454 -#define CONFIG_SPL_JR0_LIODN_NS 458 +#define CFG_SPL_PPAACT_ADDR 0x2e000000 +#define CFG_SPL_SPAACT_ADDR 0x2f000000 +#define CFG_SPL_JR0_LIODN_S 454 +#define CFG_SPL_JR0_LIODN_NS 458 #endif /* ifdef CONFIG_SPL_BUILD */ #ifndef CONFIG_SPL_BUILD diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 1df0822e9d7..7b392b06bcb 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -41,8 +41,8 @@ static ulong get_sp (void); extern void ft_fixup_num_cores(void *blob); static void set_clocks_in_mhz (struct bd_info *kbd); -#ifndef CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE -#define CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE (768*1024*1024) +#ifndef CFG_SYS_LINUX_LOWMEM_MAX_SIZE +#define CFG_SYS_LINUX_LOWMEM_MAX_SIZE (768*1024*1024) #endif static void boot_jump_linux(struct bootm_headers *images) @@ -133,7 +133,7 @@ void arch_lmb_reserve(struct lmb *lmb) #endif size = min(bootm_size, get_effective_memsize()); - size = min(size, (ulong)CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE); + size = min(size, (ulong)CFG_SYS_LINUX_LOWMEM_MAX_SIZE); if (size < bootm_size) { ulong base = bootmap_base + size; diff --git a/arch/powerpc/lib/interrupts.c b/arch/powerpc/lib/interrupts.c index bdb8030c27f..df312dfa28e 100644 --- a/arch/powerpc/lib/interrupts.c +++ b/arch/powerpc/lib/interrupts.c @@ -17,8 +17,8 @@ #include <asm/ptrace.h> #ifndef CONFIG_MPC83XX_TIMER -#ifndef CONFIG_SYS_WATCHDOG_FREQ -#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2) +#ifndef CFG_SYS_WATCHDOG_FREQ +#define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2) #endif static unsigned decrementer_count; /* count value for 1e6/HZ microseconds */ @@ -80,7 +80,7 @@ void timer_interrupt(struct pt_regs *regs) timestamp++; #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) - if (CONFIG_SYS_WATCHDOG_FREQ && (timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) + if (CFG_SYS_WATCHDOG_FREQ && (timestamp % (CFG_SYS_WATCHDOG_FREQ)) == 0) schedule(); #endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index edafad36b38..56c5da86e86 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -93,7 +93,7 @@ #define DEFAULT_RSTVEC 0x00001000 #define DEFAULT_NMIVEC 0x00001004 #define DEFAULT_MTVEC 0x00001010 -#define CONFIG_STRING_ADDR 0x0000100C +#define CFG_STRING_ADDR 0x0000100C #define EXT_IO_BASE 0x40000000 #define DRAM_BASE 0x80000000 diff --git a/arch/x86/include/asm/acpi/chromeos.asl b/arch/x86/include/asm/acpi/chromeos.asl index 2a0fd33265d..4fb13f34d42 100644 --- a/arch/x86/include/asm/acpi/chromeos.asl +++ b/arch/x86/include/asm/acpi/chromeos.asl @@ -5,7 +5,7 @@ #ifdef CONFIG_CHROMEOS -#define CONFIG_VBOOT_VBNV_OFFSET 0x26 +#define CFG_VBOOT_VBNV_OFFSET 0x26 #include <asm/acpi/vbnv_layout.h> @@ -68,7 +68,7 @@ Device (CRHW) Name(VNBV, Package() { // See src/vendorcode/google/chromeos/Kconfig // for the definition of these: - CONFIG_VBOOT_VBNV_OFFSET, + CFG_VBOOT_VBNV_OFFSET, VBOOT_VBNV_BLOCK_SIZE }) Return(VNBV) |