diff options
| author | Simon Glass | 2016-01-21 19:43:36 -0700 |
|---|---|---|
| committer | Simon Glass | 2016-01-21 20:42:34 -0700 |
| commit | 79d020ee74241251c0888a3badae9666e457eb6d (patch) | |
| tree | f6f09150767519ffde7d8cfb95a5075f62f4f988 /arch | |
| parent | ec4ac4e7c07fb76f8d0ae5e0f1670f6f879618a6 (diff) | |
rockchip: Use pwrseq for MMC start-up on jerry
This is defined in the device tree in Linux. Copy over the settings so that
this can be used instead of hard-coding the reset line.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/rk3288-veyron.dtsi | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi index 7e37158fc35..12404ff76b9 100644 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ b/arch/arm/dts/rk3288-veyron.dtsi @@ -106,6 +106,13 @@ priority = /bits/ 8 <200>; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + }; + sound { compatible = "rockchip,rockchip-audio-max98090"; rockchip,model = "ROCKCHIP-I2S"; @@ -259,11 +266,12 @@ bus-width = <8>; cap-mmc-highspeed; mmc-hs200-1_8v; + mmc-pwrseq = <&emmc_pwrseq>; disable-wp; non-removable; num-slots = <1>; pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_deassert_reset>; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>; status = "okay"; }; @@ -671,9 +679,8 @@ }; emmc { - /* Make sure eMMC is not in reset */ - emmc_deassert_reset: emmc-deassert-reset { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_up>; + emmc_reset: emmc-reset { + rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; }; /* |