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authorOoi, Joyce2019-11-21 06:48:56 -0800
committerMarek Vasut2019-11-22 03:08:12 +0100
commit7dad444c765ab94bf70592c502df9d1e1f72d436 (patch)
treee63b417eecb5c27a546648d2d88f39fe760e52ba /arch
parent48f23dd6a410d84499c9de1ae16dde9d10cb5fc7 (diff)
arm: dts: Stratix10: change pad skew values for EMAC0 PHY driver
The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA drive strength has caused CE test to fail. This requires changes on the pad skew for EMAC0 PHY driver. Based on several measurements done, Tx clock does not require the extra 0.96ns delay which was needed in Arria10. Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch')
-rwxr-xr-xarch/arm/dts/socfpga_stratix10_socdk.dts2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
index ce07659602b..58baa710d40 100755
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -73,7 +73,7 @@
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
- txc-skew-ps = <1860>; /* 960ps */
+ txc-skew-ps = <900>; /* 0ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
};