arm: include: imx: Remove duplicate newlines

Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

13 files changed, 0 insertions, 22 deletions

diff --git a/arch/arm/include/asm/arch-mx27/gpio.h b/arch/arm/include/asm/arch-mx27/gpio.h
index 9f342eb7f71..af05d1eb887 100644
--- a/arch/arm/include/asm/arch-mx27/gpio.h
+++ b/arch/arm/include/asm/arch-mx27/gpio.h
@@ -4,7 +4,6 @@
  * Philippe Reynes <tremyfr@yahoo.fr>
  */
 
-
 #ifndef __ASM_ARCH_MX27_GPIO_H
 #define __ASM_ARCH_MX27_GPIO_H
 
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
index 77794d7d03d..60499189b2c 100644
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -236,7 +236,6 @@ struct fuse_bank0_regs {
 #define SDCS1_SEL	(1 << 1)
 #define SDCS0_SEL	(1 << 0)
 
-
 /* important definition of some bits of WCR */
 #define WCR_WDE 0x04
 
diff --git a/arch/arm/include/asm/arch-mx31/gpio.h b/arch/arm/include/asm/arch-mx31/gpio.h
index 45e9fc61937..1bfe28f95c9 100644
--- a/arch/arm/include/asm/arch-mx31/gpio.h
+++ b/arch/arm/include/asm/arch-mx31/gpio.h
@@ -4,7 +4,6 @@
  * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
  */
 
-
 #ifndef __ASM_ARCH_MX31_GPIO_H
 #define __ASM_ARCH_MX31_GPIO_H
 
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index a0ab3a0e665..a608732f765 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -585,7 +585,6 @@ struct esdc_regs {
 #define GET_PLL_MFI(x)		(((x) >> 10) & 0xf)
 #define GET_PLL_MFN(x)		(((x) >> 0) & 0x3ff)
 
-
 #define WEIM_ESDCTL0	0xB8001000
 #define WEIM_ESDCFG0	0xB8001004
 #define WEIM_ESDCTL1	0xB8001008
@@ -777,7 +776,6 @@ struct esdc_regs {
 #define MUX_CTL_NFC_ALE		0xD6
 #define MUX_CTL_NFC_CLE		0xD7
 
-
 #define MUX_CTL_CAPTURE		0x150
 #define MUX_CTL_COMPARE		0x151
 
diff --git a/arch/arm/include/asm/arch-mx5/gpio.h b/arch/arm/include/asm/arch-mx5/gpio.h
index dad40bd3d7e..98f9d63e9a8 100644
--- a/arch/arm/include/asm/arch-mx5/gpio.h
+++ b/arch/arm/include/asm/arch-mx5/gpio.h
@@ -4,7 +4,6 @@
  * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
  */
 
-
 #ifndef __ASM_ARCH_MX5_GPIO_H
 #define __ASM_ARCH_MX5_GPIO_H
 
diff --git a/arch/arm/include/asm/arch-mx6/gpio.h b/arch/arm/include/asm/arch-mx6/gpio.h
index b3913199337..f5c8d336991 100644
--- a/arch/arm/include/asm/arch-mx6/gpio.h
+++ b/arch/arm/include/asm/arch-mx6/gpio.h
@@ -4,7 +4,6 @@
  * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
  */
 
-
 #ifndef __ASM_ARCH_MX6_GPIO_H
 #define __ASM_ARCH_MX6_GPIO_H
 
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 8fd3dd2df3a..7f216c70e8b 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -385,7 +385,6 @@
 			  ((is_mx6ull()) ?	\
 			  MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
 
-
 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 
 #define SRC_SCR_CORE_1_RESET_OFFSET     14
diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h
index bfa68a9d2a0..bb2642d46c8 100644
--- a/arch/arm/include/asm/arch-mx7/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx7/crm_regs.h
@@ -229,7 +229,6 @@ struct mxc_ccm_anatop_reg {
 #define ANADIG_PLL_ENET_PWDN_MASK			(0x01 << 5)
 #define ANADIG_PLL_VIDEO_PWDN_MASK			(0x01 << 12)
 
-
 #define ANATOP_PFD480B_PFD4_FRAC_MASK			0x0000003f
 #define ANATOP_PFD480B_PFD4_FRAC_320M_VAL		0x0000001B
 #define ANATOP_PFD480B_PFD4_FRAC_392M_VAL		0x00000016
@@ -1784,7 +1783,6 @@ struct mxc_ccm_anatop_reg {
 #define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT       24
 #define PMU_LOWPWR_CTRL_TOG_CONTROL1(x)          (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK)
 
-
 /* HW_ANADIG_TEMPSENSE0 Bit Fields */
 #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu
 #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0
@@ -1998,7 +1996,6 @@ struct mxc_ccm_anatop_reg {
 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29
 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK)
 
-
 #define CCM_GPR(i)		(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i))
 #define CCM_OBSERVE(i)		(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i))
 #define CCM_SCTRL(i)		(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i))
@@ -2091,7 +2088,6 @@ struct mxc_ccm_anatop_reg {
 #define CLK_ROOT_ALT6		0x06000000
 #define CLK_ROOT_ALT7		0x07000000
 
-
 #define DRAM_CLK_ROOT_POST_DIV_MASK	0x00000007
 #define CLK_ROOT_POST_DIV_MASK	0x0000003f
 #define CLK_ROOT_POST_DIV_SHIFT	0
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index 6f5ae5173c0..849c5482241 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -71,7 +71,6 @@
 #define GLOBAL_TIMER_BASE_ADDR          (ARM_PERIPHBASE + 0x0200)
 #define PRIVATE_TIMERS_WD_BASE_ADDR     (ARM_PERIPHBASE + 0x0600)
 
-
 /* Defines for Blocks connected via AIPS (SkyBlue) */
 #define AIPS_TZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
 #define AIPS_TZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
@@ -1162,7 +1161,6 @@ struct rdc_sema_regs {
 #define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK		0x3ffff
 #define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET		0
 
-
 extern void check_cpu_temperature(void);
 
 extern void pcie_power_up(void);
diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
index 33a699ff71a..02e434f2e65 100644
--- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
@@ -124,7 +124,6 @@
 #define IOMUXC_PSMI_IMUX_ALT6		(0x6)
 #define IOMUXC_PSMI_IMUX_ALT7		(0x7)
 
-
 #define SIM_SOPT1_EN_SNVS_HARD_RST	(1<<8)
 #define SIM_SOPT1_PMIC_STBY_REQ		(1<<2)
 #define SIM_SOPT1_A7_SW_RESET		(1<<0)
@@ -240,7 +239,6 @@
 #define IOMUXC_DPCR_DDR_DQS2	((IOMUXC_DDR_RBASE + (4 * 34)))
 #define IOMUXC_DPCR_DDR_DQS3	((IOMUXC_DDR_RBASE + (4 * 35)))
 
-
 #define IOMUXC_DPCR_DDR_DQ0	((IOMUXC_DDR_RBASE + (4 * 0)))
 #define IOMUXC_DPCR_DDR_DQ1	((IOMUXC_DDR_RBASE + (4 * 1)))
 #define IOMUXC_DPCR_DDR_DQ2	((IOMUXC_DDR_RBASE + (4 * 2)))
diff --git a/arch/arm/include/asm/arch-mx7ulp/iomux.h b/arch/arm/include/asm/arch-mx7ulp/iomux.h
index f067c02062f..3eec2c78e56 100644
--- a/arch/arm/include/asm/arch-mx7ulp/iomux.h
+++ b/arch/arm/include/asm/arch-mx7ulp/iomux.h
@@ -69,7 +69,6 @@ typedef u64 iomux_cfg_t;
 #define NEW_PAD_CTRL(cfg, pad)	(((cfg) & ~MUX_PAD_CTRL_MASK) | \
 					MUX_PAD_CTRL(pad))
 
-
 #define IOMUX_CONFIG_MPORTS       0x20
 #define MUX_MODE_MPORTS           ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \
 				MUX_MODE_SHIFT)
@@ -87,7 +86,6 @@ typedef u64 iomux_cfg_t;
 #define PAD_CTL_PUS_UP       ((1 << 0) | PAD_CTL_PUE)
 #define PAD_CTL_PUS_DOWN     ((0 << 0) | PAD_CTL_PUE)
 
-
 void mx7ulp_iomux_setup_pad(iomux_cfg_t pad);
 void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list,
 				      unsigned count);
diff --git a/arch/arm/include/asm/arch-mx7ulp/pcc.h b/arch/arm/include/asm/arch-mx7ulp/pcc.h
index 8f0d7006286..09b9b9b8f34 100644
--- a/arch/arm/include/asm/arch-mx7ulp/pcc.h
+++ b/arch/arm/include/asm/arch-mx7ulp/pcc.h
@@ -278,7 +278,6 @@ enum pcc3_entry {
 	RSVD127_PCC3_SLOT		= 127,
 };
 
-
 /* PCC registers */
 #define PCC_PR_OFFSET	31
 #define PCC_PR_MASK		(0x1 << PCC_PR_OFFSET)
@@ -293,7 +292,6 @@ enum pcc3_entry {
 #define PCC_PCD_OFFSET	0
 #define PCC_PCD_MASK	(0x7 << PCC_PCD_OFFSET)
 
-
 enum pcc_clksrc_type {
 	CLKSRC_PER_PLAT = 0,
 	CLKSRC_PER_BUS = 1,
@@ -353,7 +351,6 @@ enum pcc_clk {
 	PER_CLK_GPU2D,
 };
 
-
 /* This structure keeps info for each pcc slot */
 struct pcc_entry {
 	u32 pcc_base;
diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h
index 3b5b7f6803c..57e9fb2a27c 100644
--- a/arch/arm/include/asm/arch-mx7ulp/scg.h
+++ b/arch/arm/include/asm/arch-mx7ulp/scg.h
@@ -145,7 +145,6 @@
 
 #define SCG_UPLL_CSR_UPLLVLD_MASK       (0x01000000)
 
-
 #define SCG_PLL_PFD3_GATE_MASK          (0x80000000)
 #define SCG_PLL_PFD2_GATE_MASK          (0x00800000)
 #define SCG_PLL_PFD1_GATE_MASK          (0x00008000)