arm64: zynqmp: Add x-prc-01/02/03/04/05 revA support from SC

Add i2c accessible devices with description.
There is versal specific eeprom and i2c-gpio controller.

SE3 has also clock chip present.

Also remove x-prc description from SC dts.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4f71ec6a63240fd4aaa3453824138281c50d71c3.1695808407.git.michal.simek@amd.com

6 files changed, 409 insertions, 0 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e060081cdea..d1b28a6d02e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -401,6 +401,11 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-m-a2197-02-revA.dtb		\
 	zynqmp-m-a2197-03-revA.dtb		\
 	zynqmp-p-a2197-00-revA.dtb		\
+	zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo	\
+	zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo	\
+	zynqmp-p-a2197-00-revA-x-prc-03-revA.dtbo	\
+	zynqmp-p-a2197-00-revA-x-prc-04-revA.dtbo	\
+	zynqmp-p-a2197-00-revA-x-prc-05-revA.dtbo	\
 	zynqmp-mini.dtb				\
 	zynqmp-mini-emmc0.dtb			\
 	zynqmp-mini-emmc1.dtb			\
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso
new file mode 100644
index 00000000000..197dc252353
--- /dev/null
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP System Controller X-PRC-01 revA (SE1)
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+	compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01";
+
+	fragment@0 {
+		target = <&dc_i2c>;
+
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			x_prc_eeprom: eeprom@52 { /* u120 */
+				compatible = "atmel,24c02";
+				reg = <0x52>;
+			};
+
+			x_prc_tca9534: gpio@22 { /* u121 tca9534 */
+				compatible = "nxp,pca9534";
+				reg = <0x22>;
+				gpio-controller; /* IRQ not connected */
+				#gpio-cells = <2>;
+				gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+						  "", "", "", "";
+				gtr-sel0 {
+					gpio-hog;
+					gpios = <0 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_1";
+				};
+				gtr-sel1 {
+					gpio-hog;
+					gpios = <1 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_2";
+				};
+				gtr-sel2 {
+					gpio-hog;
+					gpios = <2 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_3";
+				};
+				gtr-sel3 {
+					gpio-hog;
+					gpios = <3 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_4";
+				};
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&i2c1>; /* Must be enabled via J242 */
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			eeprom_versal: eeprom@51 { /* u116 */
+				compatible = "atmel,24c02";
+				reg = <0x51>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso
new file mode 100644
index 00000000000..8eb6e40dd9d
--- /dev/null
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2)
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+	compatible = "xlnx,zynqmp-x-prc-02-revA", "xlnx,zynqmp-x-prc-02";
+
+	fragment@0 {
+		target = <&dc_i2c>;
+
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			x_prc_eeprom: eeprom@52 { /* u16 */
+				compatible = "atmel,24c02";
+				reg = <0x52>;
+			};
+
+			x_prc_tca9534: gpio@22 { /* u17 tca9534 */
+				compatible = "nxp,pca9534";
+				reg = <0x22>;
+				gpio-controller; /* IRQ not connected */
+				#gpio-cells = <2>;
+				gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+						  "", "", "", "";
+				gtr-sel0 {
+					gpio-hog;
+					gpios = <0 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_1";
+				};
+				gtr-sel1 {
+					gpio-hog;
+					gpios = <1 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_2";
+				};
+				gtr-sel2 {
+					gpio-hog;
+					gpios = <2 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_3";
+				};
+				gtr-sel3 {
+					gpio-hog;
+					gpios = <3 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_4";
+				};
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&i2c1>; /* Must be enabled via J242 */
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			eeprom_versal: eeprom@51 { /* u12 */
+				compatible = "atmel,24c02";
+				reg = <0x51>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso
new file mode 100644
index 00000000000..af7a3ce9c1a
--- /dev/null
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3)
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+	compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03";
+
+	fragment@0 {
+		target = <&dc_i2c>;
+
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			x_prc_eeprom: eeprom@52 { /* u1 */
+				compatible = "atmel,24c02";
+				reg = <0x52>;
+			};
+
+			x_prc_tca9534: gpio@22 { /* u3 tca9534 */
+				compatible = "nxp,pca9534";
+				reg = <0x22>;
+				gpio-controller; /* IRQ not connected */
+				#gpio-cells = <2>;
+				gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+						  "", "", "", "";
+				gtr-sel0 {
+					gpio-hog;
+					gpios = <0 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_1";
+				};
+				gtr-sel1 {
+					gpio-hog;
+					gpios = <1 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_2";
+				};
+				gtr-sel2 {
+					gpio-hog;
+					gpios = <2 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_3";
+				};
+				gtr-sel3 {
+					gpio-hog;
+					gpios = <3 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_4";
+				};
+			};
+			x_prc_si5338: clock-generator@70 { /* U9 */
+				compatible = "silabs,si5338";
+				reg = <0x70>; /* FIXME */
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&i2c1>; /* Must be enabled via J90/J91 */
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			eeprom_versal: eeprom@51 { /* u2 */
+				compatible = "atmel,24c02";
+				reg = <0x51>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso
new file mode 100644
index 00000000000..29a6c2a627b
--- /dev/null
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4)
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+	compatible = "xlnx,zynqmp-x-prc-04-revA", "xlnx,zynqmp-x-prc-04";
+
+	fragment@0 {
+		target = <&dc_i2c>;
+
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			x_prc_eeprom: eeprom@52 { /* u120 */
+				compatible = "atmel,24c02";
+				reg = <0x52>;
+			};
+
+			x_prc_tca9534: gpio@22 { /* u121 tca9534 */
+				compatible = "nxp,pca9534";
+				reg = <0x22>;
+				gpio-controller; /* IRQ not connected */
+				#gpio-cells = <2>;
+				gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+						  "", "", "", "";
+				gtr-sel0 {
+					gpio-hog;
+					gpios = <0 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_1";
+				};
+				gtr-sel1 {
+					gpio-hog;
+					gpios = <1 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_2";
+				};
+				gtr-sel2 {
+					gpio-hog;
+					gpios = <2 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_3";
+				};
+				gtr-sel3 {
+					gpio-hog;
+					gpios = <3 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_4";
+				};
+			};
+
+			si570_gem_tsu: clock-generator@5d { /* u164 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>;
+				temperature-stability = <50>;
+				factory-fout = <300000000>; /* FIXME */
+				clock-frequency = <300000000>;
+				clock-output-names = "si570_gem_tsu_clk";
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&i2c1>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			eeprom_versal: eeprom@51 { /* u153 */
+				compatible = "atmel,24c02";
+				reg = <0x51>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso
new file mode 100644
index 00000000000..6ddf18cf643
--- /dev/null
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5)
+ *
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/{
+	compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05";
+
+	fragment@0 {
+		target = <&dc_i2c>;
+
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			x_prc_eeprom: eeprom@52 { /* u120 */
+				compatible = "atmel,24c02";
+				reg = <0x52>;
+			};
+
+			x_prc_tca9534: gpio@22 { /* u121 tca9534 */
+				compatible = "nxp,pca9534";
+				reg = <0x22>;
+				gpio-controller; /* IRQ not connected */
+				#gpio-cells = <2>;
+				gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+						  "", "", "", "";
+				gtr-sel0 {
+					gpio-hog;
+					gpios = <0 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_1";
+				};
+				gtr-sel1 {
+					gpio-hog;
+					gpios = <1 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_2";
+				};
+				gtr-sel2 {
+					gpio-hog;
+					gpios = <2 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_3";
+				};
+				gtr-sel3 {
+					gpio-hog;
+					gpios = <3 0>;
+					input; /* FIXME add meaning */
+					line-name = "sw4_4";
+				};
+			};
+
+			si570_gem_tsu: clock-generator@5d { /* u164 */
+				#clock-cells = <0>;
+				compatible = "silabs,si570";
+				reg = <0x5d>;
+				temperature-stability = <50>;
+				factory-fout = <300000000>; /* FIXME */
+				clock-frequency = <300000000>;
+				clock-output-names = "si570_gem_tsu_clk";
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&i2c1>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			eeprom_versal: eeprom@51 { /* u153 */
+				compatible = "atmel,24c02";
+				reg = <0x51>;
+			};
+		};
+	};
+};