diff options
| author | Peng Fan | 2023-04-28 12:08:16 +0800 |
|---|---|---|
| committer | Stefano Babic | 2023-05-21 16:54:40 +0200 |
| commit | a6b36e99708a1b667f44287fc25084bfd735183d (patch) | |
| tree | 35f5f9a0dfcfcd0d05c09f7a4d178922e65261c5 /arch | |
| parent | 69326a7f20bd4e98eb7e310e262818fbf9c9e884 (diff) | |
imx9: add more PLL settings
Add more PLL settings for A55 and Display
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/imx9/clock.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 51aa259aa05..7d3a4c01333 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -26,6 +26,7 @@ static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR; static struct imx_intpll_rate_table imx9_intpll_tbl[] = { INT_PLL_RATE(1800000000U, 1, 150, 2), /* 1.8Ghz */ INT_PLL_RATE(1700000000U, 1, 141, 2), /* 1.7Ghz */ + INT_PLL_RATE(1500000000U, 1, 125, 2), /* 1.5Ghz */ INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */ INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */ INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */ @@ -35,8 +36,11 @@ static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = { FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */ FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */ FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */ + FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1), + FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1), FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */ FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */ + FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1), }; /* return in khz */ |