diff options
author | Tom Rini | 2023-12-18 09:56:58 -0500 |
---|---|---|
committer | Tom Rini | 2023-12-18 09:56:58 -0500 |
commit | a6f86132e30a407c7f96461df53c62fbe52e2b54 (patch) | |
tree | 95589ac17ec3ba7118c184a53a0671cabec6f2de /arch | |
parent | cd908ba1869de731a1487ec1707de0a312e746be (diff) | |
parent | 44a792c99498f5a9d3526019779d66585978c491 (diff) |
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next
- VisionFive2: Enable CONFIG_SYSRESET
- StarFive: Modify starfive timer driver
- AMD/Xilinx: Add MicroBlaze V support
- Unmatched: Migrate to text environment
Diffstat (limited to 'arch')
-rw-r--r-- | arch/riscv/Kconfig | 4 | ||||
-rw-r--r-- | arch/riscv/dts/Makefile | 2 | ||||
-rw-r--r-- | arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 5 | ||||
-rw-r--r-- | arch/riscv/dts/xilinx-mbv32.dts | 106 |
4 files changed, 117 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6d0d812ddb5..67126d96af8 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -39,6 +39,9 @@ config TARGET_TH1520_LPI4A bool "Support Sipeed's TH1520 Lichee PI 4A Board" select SYS_CACHE_SHIFT_6 +config TARGET_XILINX_MBV + bool "Support AMD/Xilinx MicroBlaze V" + endchoice config SYS_ICACHE_OFF @@ -82,6 +85,7 @@ source "board/sifive/unmatched/Kconfig" source "board/sipeed/maix/Kconfig" source "board/starfive/visionfive2/Kconfig" source "board/thead/th1520_lpi4a/Kconfig" +source "board/xilinx/mbv/Kconfig" # platform-specific options below source "arch/riscv/cpu/andesv5/Kconfig" diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index be6c8a42272..b05bb5607f0 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,6 +9,8 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb +dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb + include $(srctree)/scripts/Makefile.dts targets += $(dtb-y) diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi index e40f57a1508..e94f9fe826a 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi @@ -34,6 +34,11 @@ device_type = "memory"; reg = <0x0 0x40000000 0x2 0x0>; }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>; + }; }; &osc { diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts new file mode 100644 index 00000000000..6a6b8b694bd --- /dev/null +++ b/arch/riscv/dts/xilinx-mbv32.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for AMD MicroBlaze V + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "AMD MicroBlaze V 32bit"; + compatible = "amd,mbv"; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <102000000>; + cpu_0: cpu@0 { + compatible = "amd,mbv32", "riscv"; + device_type = "cpu"; + reg = <0>; + riscv,isa = "rv32imafdc"; + i-cache-size = <32768>; + d-cache-size = <32768>; + clock-frequency = <102000000>; + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x20000000>; + }; + + clk102: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <102000000>; + }; + + axi: axi { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + bootph-all; + + axi_intc: interrupt-controller@41200000 { + compatible = "xlnx,xps-intc-1.00.a"; + reg = <0x41200000 0x1000>; + interrupt-controller; + interrupt-parent = <&cpu0_intc>; + #interrupt-cells = <2>; + kind-of-intr = <0>; + }; + + xlnx_timer0: timer@41c00000 { + compatible = "xlnx,xps-timer-1.00.a"; + reg = <0x41c00000 0x1000>; + interrupt-parent = <&axi_intc>; + interrupts = <1 2>; + bootph-all; + xlnx,one-timer-only = <0>; + clock-names = "s_axi_aclk"; + clocks = <&clk102>; + }; + + xlnx_timer1: timer@41c20000 { + compatible = "xlnx,xps-timer-1.00.a"; + reg = <0x41c20000 0x1000>; + interrupt-parent = <&axi_intc>; + interrupts = <0 2>; + xlnx,one-timer-only = <0>; + clock-names = "s_axi_aclk"; + clocks = <&clk102>; + }; + + uart0: serial@40600000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x40600000 0x1000>; + interrupt-parent = <&axi_intc>; + interrupts = <2 2>; + bootph-all; + clocks = <&clk102>; + current-speed = <115200>; + xlnx,data-bits = <8>; + xlnx,use-parity = <0>; + }; + }; +}; |