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authorStefan Roese2018-10-23 12:25:16 +0200
committerStefan Roese2018-11-06 13:21:13 +0100
commitae4c38a5384033c7f5584e33cce1adc511fff333 (patch)
tree3549b559da40b5c043d5e4caa6b136adefb3c581 /arch
parent6843db99224e1e94ef7ef4c1d7bce5615cd3589d (diff)
arm: mvebu: armada-xp-theadorable.dts: Change CS# for 2nd FPGA
The new board version has the 2nd FPGA connected via CS# 0 instead of 2 on SPI bus 1. Change this setup in the DT accordingly. Please note that this change does still work on the old board version because the CS signal is not used on this board. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/armada-xp-theadorable.dts4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/dts/armada-xp-theadorable.dts b/arch/arm/dts/armada-xp-theadorable.dts
index 065e4434175..965c38426c5 100644
--- a/arch/arm/dts/armada-xp-theadorable.dts
+++ b/arch/arm/dts/armada-xp-theadorable.dts
@@ -151,11 +151,11 @@
spi1: spi@10680 {
status = "okay";
- fpga@2 {
+ fpga@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-generic-device";
- reg = <2>; /* Chip select 2 */
+ reg = <0>; /* Chip select 0 */
spi-max-frequency = <27777777>;
};
};