riscv: Make start.S available for all targets

Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
common for all RISC-V targets.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

5 files changed, 4 insertions, 4 deletions

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index af432e16ff5..8fb6a889d8d 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -3,7 +3,7 @@
 # Copyright (C) 2017 Andes Technology Corporation.
 # Rick Chen, Andes Technology Corporation <rick@andestech.com>
 
-head-y := arch/riscv/cpu/$(CPU)/start.o
+head-y := arch/riscv/cpu/start.o
 
 libs-y += arch/riscv/cpu/
 libs-y += arch/riscv/cpu/$(CPU)/
diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile
index 63de163e3fb..2cc6757fcf8 100644
--- a/arch/riscv/cpu/Makefile
+++ b/arch/riscv/cpu/Makefile
@@ -2,4 +2,6 @@
 #
 # Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
 
+extra-y = start.o
+
 obj-y += cpu.o
diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile
index c3f164c1226..2ab0342fe85 100644
--- a/arch/riscv/cpu/ax25/Makefile
+++ b/arch/riscv/cpu/ax25/Makefile
@@ -3,6 +3,4 @@
 # Copyright (C) 2017 Andes Technology Corporation
 # Rick Chen, Andes Technology Corporation <rick@andestech.com>
 
-extra-y	= start.o
-
 obj-y	:= cpu.o
diff --git a/arch/riscv/cpu/ax25/start.S b/arch/riscv/cpu/start.S
index 7cd7755190c..7cd7755190c 100644
--- a/arch/riscv/cpu/ax25/start.S
+++ b/arch/riscv/cpu/start.S
diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds
index f414473e54b..11bc4a738b6 100644
--- a/arch/riscv/cpu/u-boot.lds
+++ b/arch/riscv/cpu/u-boot.lds
@@ -11,7 +11,7 @@ SECTIONS
 {
 	. = ALIGN(4);
 	.text : {
-		arch/riscv/cpu/ax25/start.o	(.text)
+		arch/riscv/cpu/start.o	(.text)
 	}
 
 	/* This needs to come before *(.text*) */