diff options
| author | Marek Vasut | 2019-11-26 09:34:52 +0100 |
|---|---|---|
| committer | Stefano Babic | 2020-01-07 10:26:56 +0100 |
| commit | c35b19531dd0c283a1b28ae937c764c4be59c8b3 (patch) | |
| tree | 0dbab971953b077217b1bccb794dd74436572b0e /arch | |
| parent | b314003fda6e398c5acdd691e4f39d50c1810bce (diff) | |
ARM: mx6: ddr: Add support for iMX6SX
This patch adds support for iMX6SX MMDC into the DDR calibration
code. The only difference between MX6DQ and MX6SX is that the SX
has 2 SDQS registers, while the DQ has 8.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Eric Nelson <eric@nelint.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/mx6/ddr.c | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index b2402f75db7..8ed8b79c8b7 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -247,12 +247,22 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo) static void mmdc_set_sdqs(bool set) { - struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux = + struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE; - u32 sdqs = (u32)(&mx6_ddr_iomux->dram_sdqs0); - int i; + struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux = + (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE; + int i, sdqs_cnt; + u32 sdqs; + + if (is_mx6sx()) { + sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0); + sdqs_cnt = 2; + } else { /* MX6DQ */ + sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0); + sdqs_cnt = 8; + } - for (i = 0; i < 8; i++) { + for (i = 0; i < sdqs_cnt; i++) { if (set) setbits_le32(sdqs + (4 * i), 0x7000); else |