diff options
| author | Marek Vasut | 2021-09-14 05:25:34 +0200 |
|---|---|---|
| committer | Marek Vasut | 2021-09-22 21:30:39 +0200 |
| commit | c3880e65975bd40ba025b9fafa5732a98ea9e736 (patch) | |
| tree | 485152d0af3262283b6c75f67652e40359644563 /arch | |
| parent | e21bbffa1d6d2634dabee393dd342764e2931441 (diff) | |
arm: socfpga: vining: Fix UDC controller phandle in DT
The USB peripheral controller is the DWC2 controller 1, not 0.
Update the phandle to fix UDC support on this board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index 9e8be282005..fb05c31d87b 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -11,7 +11,7 @@ /{ aliases { spi0 = "/soc/spi@ff705000"; - udc0 = &usb0; + udc0 = &usb1; }; }; |