diff options
| author | Marek Vasut | 2018-04-04 23:32:44 +0200 |
|---|---|---|
| committer | Marek Vasut | 2018-04-11 23:11:54 +0200 |
| commit | c670607331dbdfdf74a52117b96426c50de9ecd0 (patch) | |
| tree | 5d0a2146128dd7b35213d0f5a50f85dd1a6044c7 /arch | |
| parent | ce19d4ca7dc43ff053d2a06f4bed9696cee97902 (diff) | |
ARM: rmobile: Do not init caches in TPL before DRAM
Skip the cache initialization, which can be done later on in U-Boot
proper, since this interferes with early DRAM initialization in TPL.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-rmobile/lowlevel_init_ca15.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-rmobile/lowlevel_init_ca15.S b/arch/arm/mach-rmobile/lowlevel_init_ca15.S index a5dbbea9e15..ef2280bea42 100644 --- a/arch/arm/mach-rmobile/lowlevel_init_ca15.S +++ b/arch/arm/mach-rmobile/lowlevel_init_ca15.S @@ -11,6 +11,7 @@ #include <linux/linkage.h> ENTRY(lowlevel_init) +#ifndef CONFIG_TPL_BUILD mrc p15, 0, r4, c0, c0, 5 /* mpidr */ orr r4, r4, r4, lsr #6 and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */ @@ -83,6 +84,7 @@ _exit_init_l2_a15: bl s_init ldr lr, [sp] +#endif mov pc, lr nop ENDPROC(lowlevel_init) |