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authorTom Rini2020-08-13 08:25:25 -0400
committerTom Rini2020-08-13 08:25:25 -0400
commitcdcf591d9b20534e5f5c58aa2a2b07b3b173f5a1 (patch)
tree0afbaedfc98d6f15488f039400c5853432313766 /arch
parent6808dc62d75de706c5aabc24e36caf52ead30fc7 (diff)
parentac5cd429e3cc892f717075422c4b9c2c29ff8f18 (diff)
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Fix dtc warnings for some MVEBU boards
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/armada-3720-turris-mox.dts2
-rw-r--r--arch/arm/dts/armada-388-gp.dts2
-rw-r--r--arch/arm/dts/armada-xp-maxbcm.dts3
-rw-r--r--arch/arm/dts/armada-xp-theadorable.dts2
4 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts
index a1e0ad50204..0f0a6ce65d8 100644
--- a/arch/arm/dts/armada-3720-turris-mox.dts
+++ b/arch/arm/dts/armada-3720-turris-mox.dts
@@ -100,6 +100,8 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
rtc@6f {
compatible = "microchip,mcp7941x";
diff --git a/arch/arm/dts/armada-388-gp.dts b/arch/arm/dts/armada-388-gp.dts
index d5ad2fd7e22..d59aa5f232d 100644
--- a/arch/arm/dts/armada-388-gp.dts
+++ b/arch/arm/dts/armada-388-gp.dts
@@ -72,6 +72,8 @@
pinctrl-0 = <&spi0_pins>;
status = "okay";
u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <0>;
spi-flash@0 {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/armada-xp-maxbcm.dts b/arch/arm/dts/armada-xp-maxbcm.dts
index 921eb708625..d2b07f74cf5 100644
--- a/arch/arm/dts/armada-xp-maxbcm.dts
+++ b/arch/arm/dts/armada-xp-maxbcm.dts
@@ -177,6 +177,9 @@
};
mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
phy0: ethernet-phy@0 {
reg = <0>;
};
diff --git a/arch/arm/dts/armada-xp-theadorable.dts b/arch/arm/dts/armada-xp-theadorable.dts
index 5b18d62c3c5..6a1df870ab5 100644
--- a/arch/arm/dts/armada-xp-theadorable.dts
+++ b/arch/arm/dts/armada-xp-theadorable.dts
@@ -107,6 +107,8 @@
};
mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};