Merge branch 'for-2024.07' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx

This pull request adds support for temperature sensors et FPGA loading
on boards from CS GROUP France.

CI: https://source.denx.de/u-boot/custodians/u-boot-mpc8xx/-/pipelines/20416

4 files changed, 74 insertions, 7 deletions

diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index aac4203a6e4..d1abe8f00bf 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -92,6 +92,12 @@ void cpu_init_f(immap_t __iomem *immr)
 				CONFIG_SYS_PLPRCR);
 #endif
 
+	/* Set SDMA configuration register */
+	if (IS_ENABLED(CONFIG_MPC885))
+		out_be32(&immr->im_siu_conf.sc_sdcr, 0x0040);
+	else
+		out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001);
+
 	/*
 	 * Memory Controller:
 	 */
diff --git a/arch/powerpc/dts/cmpc885.dts b/arch/powerpc/dts/cmpc885.dts
index 7b9566a0fa4..454ceb91ca0 100644
--- a/arch/powerpc/dts/cmpc885.dts
+++ b/arch/powerpc/dts/cmpc885.dts
@@ -83,13 +83,23 @@
 		spi: spi@aa0 {
 			status = "okay";
 			#address-cells = <1>;
-			#size-cells = <1>;
-			cell-index = <0>;
+			#size-cells = <0>;
 			compatible = "fsl,mpc8xx-spi";
-			gpios = <&CPM1_PIO_B 21 1>; /* /EEPROM_CS ACTIVE_LOW */
+			gpios = <&CPM1_PIO_B 21 1	/* /EEPROM_CS ACTIVE_LOW */
+				 &CPM1_PIO_B 23 1	/* Temperature mother board */
+				 &CPM1_PIO_B 14 1>;	/* Temperature CPU board */
 
 			eeprom@0 {
-				cell-index = <1>;
+				reg = <0>;
+				compatible = "atmel,at25", "cs,eeprom";
+			};
+			temp@1 {
+				reg = <1>;
+				compatible = "ti,lm74";
+			};
+			temp@2 {
+				reg = <2>;
+				compatible = "ti,lm74";
 			};
 		};
 	};
diff --git a/arch/powerpc/dts/cmpcpro.dts b/arch/powerpc/dts/cmpcpro.dts
index c27d9dba335..1dfa864ebba 100644
--- a/arch/powerpc/dts/cmpcpro.dts
+++ b/arch/powerpc/dts/cmpcpro.dts
@@ -140,11 +140,21 @@
 			compatible = "fsl,mpc832x-spi";
 			reg = <0x4c0 0x40>;
 			mode = "cpu";
-			gpios = <&qe_pio_d 3 1>;
+			gpios = <&qe_pio_d 3 1
+				 &qe_pio_c 5 1		/* TEMP mother board */
+				 &qe_pio_c 3 1>;	/* TEMP CPU board */
 			clock-frequency = <0>;
-			eeprom@3 {
+			eeprom@0 {
+				reg = <0>;
 				compatible = "atmel,at25", "cs,eeprom";
-				cell-index = <1>;
+			};
+			temp@1 {
+				reg = <1>;
+				compatible = "ti,lm74";
+			};
+			temp@2 {
+				reg = <2>;
+				compatible = "ti,lm74";
 			};
 		};
 		eth0: ucc@3000 {
diff --git a/arch/powerpc/dts/mcr3000.dts b/arch/powerpc/dts/mcr3000.dts
index c4d7737bc67..aa46007b8d9 100644
--- a/arch/powerpc/dts/mcr3000.dts
+++ b/arch/powerpc/dts/mcr3000.dts
@@ -26,6 +26,47 @@
 			timeout-sec = <2>;
 			hw_margin_ms = <1000>;
 		};
+
+		spi: spi@aa0 {
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl,mpc8xx-spi";
+			gpios = <&csspi 2 0
+				 &csspi 0 0>;
+
+			temp@0 {
+				reg = <0>;
+				compatible = "ti,lm74";
+			};
+			fpga@1 {
+				reg = <1>;
+			};
+		};
+	};
+
+	localbus@ff000100 {
+		compatible = "s3k,mcr3000-localbus", "fsl,pq1-localbus", "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		reg = <0xff000100 0x40>;		// ORx and BRx register
+
+		ranges = <0 0 0x04000000 0x04000000 // BOOT
+			  1 0 0x00000000 0x04000000 // SDRAM
+			  2 0 0x08000000 0x04000000 // RAMDP
+			  3 0 0x0C000000 0x04000000 // NAND
+			  4 0 0x10000000 0x04000000 // Periphs
+			  5 0 0x14000000 0x04000000 // FPGA
+			  6 0 0x18000000 0x04000000 // mezzanine
+			  7 0 0x1c000000 0x04000000>; // DSP
+
+		csspi: gpio-controller@2 {
+			#gpio-cells = <2>;
+			compatible = "s3k,mcr3000-cpld-csspi";
+			reg = <4 0x802 2>;
+			gpio-controller;
+		};
 	};
 
 	SERIAL: smc@0 {