diff options
| author | Marek Vasut | 2021-04-10 00:16:06 +0200 |
|---|---|---|
| committer | Marek Vasut | 2021-04-18 04:29:36 +0200 |
| commit | d78f7d8199ba6b6137e0c2d371171f5798148499 (patch) | |
| tree | a3bed66f829c445160d7fb26fe5bd7bbd40aa5f1 /arch | |
| parent | f0e10e33e5978515c878e1ec18952ccdd1bf5a83 (diff) | |
ARM: dts: imx8mn: Add power domain nodes
Add power domain nodes to DT.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/imx8mn.dtsi | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi index 63005ce9d1e..edcb415b53d 100644 --- a/arch/arm/dts/imx8mn.dtsi +++ b/arch/arm/dts/imx8mn.dtsi @@ -4,6 +4,8 @@ */ #include <dt-bindings/clock/imx8mn-clock.h> +#include <dt-bindings/power/imx8mn-power.h> +#include <dt-bindings/reset/imx8mq-reset.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -612,6 +614,54 @@ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mn-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_hsiomix: power-domain@0 { + #power-domain-cells = <0>; + reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>; + clocks = <&clk IMX8MN_CLK_USB_BUS>; + }; + + pgc_otg1: power-domain@1 { + #power-domain-cells = <0>; + reg = <IMX8MN_POWER_DOMAIN_OTG1>; + power-domains = <&pgc_hsiomix>; + }; + + pgc_gpumix: power-domain@2 { + #power-domain-cells = <0>; + reg = <IMX8MN_POWER_DOMAIN_GPUMIX>; + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_AHB>; + resets = <&src IMX8MQ_RESET_GPU_RESET>; + }; + + dispmix_pd: power-domain@3 { + #power-domain-cells = <0>; + reg = <IMX8MN_POWER_DOMAIN_DISPMIX>; + clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + }; + + mipi_pd: power-domain@4 { + #power-domain-cells = <0>; + reg = <IMX8MN_POWER_DOMAIN_MIPI>; + power-domains = <&dispmix_pd>; + }; + }; + }; }; aips2: bus@30400000 { @@ -964,6 +1014,7 @@ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; + power-domains = <&pgc_otg1>; status = "disabled"; }; |